hdl.ir: rename .get_fragment() to .elaborate().

Closes #9.

examples/alu.py

@@ -10,7 +10,7 @@ class ALU:
         self.o   = Signal(width)
         self.co  = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         with m.If(self.sel == 0b00):
             m.d.comb += self.o.eq(self.a | self.b)
@@ -20,7 +20,7 @@ class ALU:
             m.d.comb += self.o.eq(self.a ^ self.b)
         with m.Else():
             m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/alu_hier.py

@@ -8,10 +8,10 @@ class Adder:
         self.b   = Signal(width)
         self.o   = Signal(width)
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.comb += self.o.eq(self.a + self.b)
-        return m.lower(platform)
+        return m
 
 
 class Subtractor:
@@ -20,10 +20,10 @@ class Subtractor:
         self.b   = Signal(width)
         self.o   = Signal(width)
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.comb += self.o.eq(self.a - self.b)
-        return m.lower(platform)
+        return m
 
 
 class ALU:
@@ -36,7 +36,7 @@ class ALU:
         self.add = Adder(width)
         self.sub = Subtractor(width)
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.submodules.add = self.add
         m.submodules.sub = self.sub
@@ -50,7 +50,7 @@ class ALU:
             m.d.comb += self.o.eq(self.sub.o)
         with m.Else():
             m.d.comb += self.o.eq(self.add.o)
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/arst.py

@@ -7,15 +7,15 @@ class ClockDivisor:
         self.v = Signal(factor)
         self.o = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.sync += self.v.eq(self.v + 1)
         m.d.comb += self.o.eq(self.v[-1])
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":
     ctr  = ClockDivisor(factor=16)
-    frag = ctr.get_fragment(platform=None)
+    frag = ctr.elaborate(platform=None)
     frag.add_domains(ClockDomain("sync", async_reset=True))
     main(frag, ports=[ctr.o])

examples/ctr.py

@@ -7,11 +7,11 @@ class Counter:
         self.v = Signal(width, reset=2**width-1)
         self.o = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.sync += self.v.eq(self.v + 1)
         m.d.comb += self.o.eq(self.v[-1])
-        return m.lower(platform)
+        return m
 
 
 ctr = Counter(width=16)

examples/ctr_ce.py

@@ -8,7 +8,7 @@ class Counter:
         self.o = Signal()
         self.ce = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.sync += self.v.eq(self.v + 1)
         m.d.comb += self.o.eq(self.v[-1])
@@ -16,7 +16,7 @@ class Counter:
 
 
 ctr  = Counter(width=16)
-frag = ctr.get_fragment(platform=None)
+frag = ctr.elaborate(platform=None)
 
 # print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
 print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))

examples/fsm.py

@@ -12,7 +12,7 @@ class UARTReceiver:
         self.ack  = Signal()
         self.err  = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
 
         ctr = Signal(max=self.divisor)
@@ -56,7 +56,7 @@ class UARTReceiver:
             with m.State("ERROR"):
                 pass
 
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/gpio.py

@@ -8,12 +8,12 @@ class GPIO:
         self.pins = pins
         self.bus  = bus
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
         with m.If(self.bus.we):
             m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/inst.py

@@ -9,7 +9,7 @@ class System:
         self.dat_w = Signal(8)
         self.we    = Signal()
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.submodules.cpu = Instance("CPU",
             p_RESET_ADDR=0xfff0,
@@ -18,7 +18,7 @@ class System:
             o_d_dat_w=self.dat_w,
             i_d_we   =self.we,
         )
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/mem.py

@@ -10,7 +10,7 @@ class RegisterFile:
         self.we    = Signal()
         self.mem   = Memory(width=8, depth=16, init=[0xaa, 0x55])
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.submodules.rdport = rdport = self.mem.read_port()
         m.submodules.wrport = wrport = self.mem.write_port()
@@ -21,7 +21,7 @@ class RegisterFile:
             wrport.data.eq(self.dat_w),
             wrport.en.eq(self.we),
         ]
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":

examples/pmux.py

@@ -10,7 +10,7 @@ class ParMux:
         self.c = Signal(width)
         self.o = Signal(width)
 
-    def get_fragment(self, platform):
+    def elaborate(self, platform):
         m = Module()
         with m.Switch(self.s):
             with m.Case("--1"):
@@ -21,7 +21,7 @@ class ParMux:
                 m.d.comb += self.o.eq(self.c)
             with m.Case():
                 m.d.comb += self.o.eq(0)
-        return m.lower(platform)
+        return m
 
 
 if __name__ == "__main__":