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hdl.ir: rename .get_fragment() to .elaborate().

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Closes #9.
This commit is contained in:
whitequark 2019-01-26 02:31:12 +00:00
parent 4922a73c5d
commit 4948162f33
28 changed files with 108 additions and 88 deletions
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10
nmigen/test/test_hdl_dsl.py
View file

@ -122,7 +122,7 @@ class DSLTestCase(FHDLTestCase):
m.d.sync += o1.eq(Past(i))
m.d.pix += o2.eq(Past(i))
m.d.pix += o3.eq(Past(i, domain="sync"))
f = m.lower(platform=None)
f = m.elaborate(platform=None)
self.assertRepr(f.statements, """
(
(eq (sig o1) (sample (sig i) @ sync[1]))
@ -386,7 +386,7 @@ class DSLTestCase(FHDLTestCase):
"(sig b)": "sync",
})
frag = m.lower(platform=None)
frag = m.elaborate(platform=None)
fsm = frag.find_generated("fsm")
self.assertIsInstance(fsm.state, Signal)
self.assertEqual(fsm.encoding, OrderedDict({
@ -508,10 +508,10 @@ class DSLTestCase(FHDLTestCase):
def test_submodule_wrong(self):
m = Module()
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
m.submodules.foo = 1
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
m.submodules += 1
def test_domain_named_implicit(self):
@ -533,7 +533,7 @@ class DSLTestCase(FHDLTestCase):
m2.d.sync += self.c3.eq(self.s3)
m1.submodules.foo = m2
f1 = m1.lower(platform=None)
f1 = m1.elaborate(platform=None)
self.assertRepr(f1.statements, """
(
(eq (sig c1) (sig s1))

4
nmigen/test/test_hdl_ir.py
View file

@ -474,8 +474,8 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
def setUp_memory(self):
self.m = Memory(width=8, depth=4)
self.fr = self.m.read_port().get_fragment(platform=None)
self.fw = self.m.write_port().get_fragment(platform=None)
self.fr = self.m.read_port().elaborate(platform=None)
self.fw = self.m.write_port().elaborate(platform=None)
self.f1 = Fragment()
self.f2 = Fragment()
self.f2.add_subfragment(self.fr)

8
nmigen/test/test_lib_coding.py
View file

@ -88,7 +88,7 @@ class ReversibleSpec:
self.decoder_cls = decoder_cls
self.coder_args = args
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
enc, dec = self.encoder_cls(*self.coder_args), self.decoder_cls(*self.coder_args)
m.submodules += enc, dec
@ -96,7 +96,7 @@ class ReversibleSpec:
dec.i.eq(enc.o),
Assert(enc.i == dec.o)
]
return m.lower(platform)
return m
class HammingDistanceSpec:
@ -105,7 +105,7 @@ class HammingDistanceSpec:
self.encoder_cls = encoder_cls
self.coder_args = args
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
enc1, enc2 = self.encoder_cls(*self.coder_args), self.encoder_cls(*self.coder_args)
m.submodules += enc1, enc2
@ -113,7 +113,7 @@ class HammingDistanceSpec:
Assume(enc1.i + 1 == enc2.i),
Assert(sum(enc1.o ^ enc2.o) == self.distance)
]
return m.lower(platform)
return m
class GrayCoderTestCase(FHDLTestCase):

14
nmigen/test/test_lib_fifo.py
View file

@ -11,7 +11,7 @@ from ..lib.fifo import *
class FIFOSmokeTestCase(FHDLTestCase):
def assertSyncFIFOWorks(self, fifo, xfrm=lambda x: x):
with Simulator(xfrm(fifo.get_fragment(None)), vcd_file=open("test.vcd", "w")) as sim:
with Simulator(xfrm(Fragment.get(fifo, None)), vcd_file=open("test.vcd", "w")) as sim:
sim.add_clock(1e-6)
def process():
yield from fifo.write(1)
@ -58,7 +58,7 @@ class FIFOModel(FIFOInterface):
self.replace = Signal()
self.level = Signal(max=self.depth + 1)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
storage = Memory(self.width, self.depth)
@ -101,7 +101,7 @@ class FIFOModel(FIFOInterface):
m.d.comb += Assert(ResetSignal(self.rdomain) == ResetSignal(self.wdomain))
return m.lower(platform)
return m
class FIFOModelEquivalenceSpec:
@ -116,7 +116,7 @@ class FIFOModelEquivalenceSpec:
self.rdomain = rdomain
self.wdomain = wdomain
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.dut = dut = self.fifo
m.submodules.gold = gold = FIFOModel(dut.width, dut.depth, dut.fwft,
@ -145,7 +145,7 @@ class FIFOModelEquivalenceSpec:
Past(dut.re, domain=self.rdomain))
.implies(dut.dout == gold.dout))
return m.lower(platform)
return m
class FIFOContractSpec:
@ -160,7 +160,7 @@ class FIFOContractSpec:
self.wdomain = wdomain
self.bound = bound
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.dut = fifo = self.fifo
@ -224,7 +224,7 @@ class FIFOContractSpec:
m.d.comb += Assume(Rose(ClockSignal(self.wdomain)) |
Rose(ClockSignal(self.rdomain)))
return m.lower(platform)
return m
class FIFOFormalCase(FHDLTestCase):

2
nmigen/test/test_sim.py
View file

@ -238,7 +238,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
class SimulatorIntegrationTestCase(FHDLTestCase):
@contextmanager
def assertSimulation(self, module, deadline=None):
with Simulator(module.lower(platform=None)) as sim:
with Simulator(module.elaborate(platform=None)) as sim:
yield sim
if deadline is None:
sim.run()

3
nmigen/test/tools.py
View file

@ -9,6 +9,7 @@ import warnings
from contextlib import contextmanager
from ..hdl.ast import *
from ..hdl.ir import *
from ..back import rtlil
@ -90,7 +91,7 @@ class FHDLTestCase(unittest.TestCase):
mode=mode,
depth=depth,
script=script,
rtlil=rtlil.convert(spec.get_fragment("formal"))
rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
)
with subprocess.Popen(["sby", "-f", "-d", spec_name], cwd=spec_dir,
universal_newlines=True,