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hdl.ast: prohibit shifts by signed value.

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These are not desirable in a HDL, and currently elaborate to broken
RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like
we already do for division and modulo.

Fixes #302.
This commit is contained in:
whitequark 2020-02-01 23:04:25 +00:00
parent cce6b8687b
commit 49758a3a0c
4 changed files with 32 additions and 10 deletions
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6
nmigen/back/pysim.py
View file

@ -347,8 +347,6 @@ class _ValueCompiler(ValueVisitor, _Compiler):
helpers = {
"sign": lambda value, sign: value | sign if value & sign else value,
"zdiv": lambda lhs, rhs: 0 if rhs == 0 else lhs // rhs,
"sshl": lambda lhs, rhs: lhs << rhs if rhs >= 0 else lhs >> -rhs,
"sshr": lambda lhs, rhs: lhs >> rhs if rhs >= 0 else lhs << -rhs,
}
def on_ClockSignal(self, value):
@ -438,9 +436,9 @@ class _RHSValueCompiler(_ValueCompiler):
if value.operator == "^":
return f"({self(lhs)} ^ {self(rhs)})"
if value.operator == "<<":
return f"sshl({sign(lhs)}, {sign(rhs)})"
return f"({sign(lhs)} << {sign(rhs)})"
if value.operator == ">>":
return f"sshr({sign(lhs)}, {sign(rhs)})"
return f"({sign(lhs)} >> {sign(rhs)})"
if value.operator == "==":
return f"({sign(lhs)} == {sign(rhs)})"
if value.operator == "!=":