hdl.ast: prohibit shifts by signed value.
These are not desirable in a HDL, and currently elaborate to broken RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like we already do for division and modulo. Fixes #302.
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4 changed files with 32 additions and 10 deletions
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@ -362,15 +362,27 @@ class OperatorTestCase(FHDLTestCase):
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v1 = Const(1, 4) << Const(4)
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self.assertEqual(repr(v1), "(<< (const 4'd1) (const 3'd4))")
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self.assertEqual(v1.shape(), unsigned(11))
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v2 = Const(1, 4) << Const(-3)
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self.assertEqual(v2.shape(), unsigned(7))
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def test_shl_wrong(self):
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with self.assertRaises(NotImplementedError,
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msg="Shift by a signed value is not supported"):
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1 << Const(0, signed(6))
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with self.assertRaises(NotImplementedError,
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msg="Shift by a signed value is not supported"):
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Const(1, unsigned(4)) << -1
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def test_shr(self):
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v1 = Const(1, 4) >> Const(4)
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self.assertEqual(repr(v1), "(>> (const 4'd1) (const 3'd4))")
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self.assertEqual(v1.shape(), unsigned(4))
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v2 = Const(1, 4) >> Const(-3)
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self.assertEqual(v2.shape(), unsigned(8))
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def test_shr_wrong(self):
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with self.assertRaises(NotImplementedError,
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msg="Shift by a signed value is not supported"):
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1 << Const(0, signed(6))
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with self.assertRaises(NotImplementedError,
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msg="Shift by a signed value is not supported"):
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Const(1, unsigned(4)) << -1
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def test_lt(self):
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v = Const(0, 4) < Const(0, 6)
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@ -116,13 +116,11 @@ class SimulatorUnitTestCase(FHDLTestCase):
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stmt = lambda y, a, b: y.eq(a << b)
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self.assertStatement(stmt, [C(0b1001, 4), C(0)], C(0b1001, 5))
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self.assertStatement(stmt, [C(0b1001, 4), C(3)], C(0b1001000, 7))
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self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b10, 7))
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def test_shr(self):
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stmt = lambda y, a, b: y.eq(a >> b)
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self.assertStatement(stmt, [C(0b1001, 4), C(0)], C(0b1001, 4))
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self.assertStatement(stmt, [C(0b1001, 4), C(2)], C(0b10, 4))
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self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b100100, 5))
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def test_eq(self):
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stmt = lambda y, a, b: y.eq(a == b)
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