lib.io: make Pin an interface object.
Tracking #879. The directions of signals in `Pin` make it convenient to use a pin signature in a component, such as in: class LEDDriver(Component): pins: Out(Signature({"o": Out(1)})) led_driver = LEDDriver() connect(led_driver.pins, platform.request("led")) The `platform.request` call, correspondingly, returns a flipped `Pin` object.
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Catherine
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33c2246311
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4e078322a0
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@ -122,29 +122,36 @@ class ResourceManager:
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fields[sub.name] = resolve(sub, dir[sub.name], xdr[sub.name],
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name="{}__{}".format(name, sub.name),
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attrs={**attrs, **sub.attrs})
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return Record([
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rec = Record([
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(f_name, f.layout) for (f_name, f) in fields.items()
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], fields=fields, name=name)
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rec.signature = wiring.Signature({
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f_name: wiring.Out(f.signature) for (f_name, f) in fields.items()
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})
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return rec
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elif isinstance(resource.ios[0], (Pins, DiffPairs)):
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phys = resource.ios[0]
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# The flow is `In` below regardless of requested pin direction. The flow should
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# never be used as it's not used internally and anyone using `dir="-"` should
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# ignore it as well.
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if isinstance(phys, Pins):
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phys_names = phys.names
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port = Record([("io", len(phys))], name=name)
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port = wiring.Signature({"io": wiring.In(len(phys))}).create(path=(name,))
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if isinstance(phys, DiffPairs):
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phys_names = []
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record_fields = []
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members = {}
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if not self.should_skip_port_component(None, attrs, "p"):
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phys_names += phys.p.names
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record_fields.append(("p", len(phys)))
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members["p"] = wiring.In(len(phys))
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if not self.should_skip_port_component(None, attrs, "n"):
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phys_names += phys.n.names
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record_fields.append(("n", len(phys)))
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port = Record(record_fields, name=name)
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members["n"] = wiring.In(len(phys))
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port = wiring.Signature(members).create(path=(name,))
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if dir == "-":
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pin = None
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else:
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pin = Pin(len(phys), dir, xdr=xdr, name=name)
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pin = wiring.flipped(Pin(len(phys), dir, xdr=xdr, name=name))
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for phys_name in phys_names:
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if phys_name in self._phys_reqd:
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@ -7,6 +7,7 @@ from functools import reduce, wraps
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from .. import tracer
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from .._utils import union
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from .ast import *
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from ..lib import wiring
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__all__ = ["Direction", "DIR_NONE", "DIR_FANOUT", "DIR_FANIN", "Layout", "Record"]
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@ -132,6 +133,8 @@ class Record(ValueCastable):
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if fields is not None and field_name in fields:
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field = fields[field_name]
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if isinstance(field_shape, Layout):
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if isinstance(field, wiring.FlippedInterface):
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field = wiring.flipped(field)
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assert isinstance(field, Record) and field_shape == field.layout
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else:
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assert isinstance(field, Signal) and Shape.cast(field_shape) == field.shape()
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@ -4,18 +4,13 @@ from .. import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from ..hdl.rec import *
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from ..lib.wiring import In, Out, Signature
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__all__ = ["pin_layout", "Pin"]
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def pin_layout(width, dir, xdr=0):
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"""
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Layout of the platform interface of a pin or several pins, which may be used inside
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user-defined records.
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See :class:`Pin` for details.
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"""
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def _pin_signature(width, dir, xdr=0):
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if not isinstance(width, int) or width < 0:
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raise TypeError("Width must be a non-negative integer, not {!r}"
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.format(width))
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@ -26,29 +21,42 @@ def pin_layout(width, dir, xdr=0):
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raise TypeError("Gearing ratio must be a non-negative integer, not {!r}"
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.format(xdr))
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fields = []
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members = {}
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if dir in ("i", "io"):
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if xdr > 0:
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fields.append(("i_clk", 1))
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members["i_clk"] = In(1)
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if xdr > 2:
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fields.append(("i_fclk", 1))
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members["i_fclk"] = In(1)
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if xdr in (0, 1):
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fields.append(("i", width))
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members["i"] = In(width)
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else:
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for n in range(xdr):
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fields.append(("i{}".format(n), width))
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members["i{}".format(n)] = In(width)
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if dir in ("o", "oe", "io"):
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if xdr > 0:
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fields.append(("o_clk", 1))
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members["o_clk"] = Out(1)
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if xdr > 2:
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fields.append(("o_fclk", 1))
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members["o_fclk"] = Out(1)
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if xdr in (0, 1):
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fields.append(("o", width))
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members["o"] = Out(width)
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else:
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for n in range(xdr):
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fields.append(("o{}".format(n), width))
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members["o{}".format(n)] = Out(width)
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if dir in ("oe", "io"):
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fields.append(("oe", 1))
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members["oe"] = In(1)
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return Signature(members)
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def pin_layout(width, dir, xdr=0):
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"""
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Layout of the platform interface of a pin or several pins, which may be used inside
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user-defined records.
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See :class:`Pin` for details.
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"""
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fields = []
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for name, member in _pin_signature(width, dir, xdr).members.items():
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fields.append((name, member.shape))
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return Layout(fields)
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@ -118,3 +126,7 @@ class Pin(Record):
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super().__init__(pin_layout(self.width, self.dir, self.xdr),
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name=name, src_loc_at=src_loc_at + 1)
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@property
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def signature(self):
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return _pin_signature(self.width, self.dir, self.xdr)
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@ -6,6 +6,7 @@ from amaranth import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from amaranth.hdl.rec import *
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from amaranth.lib.wiring import *
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from amaranth.lib.io import *
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from amaranth.build.dsl import *
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from amaranth.build.res import *
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@ -62,7 +63,7 @@ class ResourceManagerTestCase(FHDLTestCase):
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r = self.cm.lookup("user_led", 0)
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user_led = self.cm.request("user_led", 0)
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self.assertIsInstance(user_led, Pin)
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self.assertIsInstance(flipped(user_led), Pin)
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self.assertEqual(user_led.name, "user_led_0")
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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@ -91,11 +92,11 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(ports[1].width, 1)
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scl_info, sda_info = self.cm.iter_single_ended_pins()
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self.assertIs(scl_info[0], i2c.scl)
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self.assertIs(flipped(scl_info[0]), i2c.scl)
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self.assertIs(scl_info[1].io, scl)
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self.assertEqual(scl_info[2], {})
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self.assertEqual(scl_info[3], False)
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self.assertIs(sda_info[0], i2c.sda)
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self.assertIs(flipped(sda_info[0]), i2c.sda)
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self.assertIs(sda_info[1].io, sda)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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@ -105,7 +106,7 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_request_diffpairs(self):
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clk100 = self.cm.request("clk100", 0)
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self.assertIsInstance(clk100, Pin)
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self.assertIsInstance(flipped(clk100), Pin)
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self.assertEqual(clk100.dir, "i")
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self.assertEqual(clk100.width, 1)
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@ -155,7 +156,6 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_request_raw(self):
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clk50 = self.cm.request("clk50", 0, dir="-")
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self.assertIsInstance(clk50, Record)
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self.assertIsInstance(clk50.io, Signal)
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ports = list(self.cm.iter_ports())
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@ -164,7 +164,6 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_request_raw_diffpairs(self):
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clk100 = self.cm.request("clk100", 0, dir="-")
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self.assertIsInstance(clk100, Record)
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self.assertIsInstance(clk100.p, Signal)
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self.assertIsInstance(clk100.n, Signal)
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