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back.verilog: detect undriven public wires using Yosys.

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This should never happen, and is certainly a logic bug in nMigen.
This commit is contained in:
whitequark 2018-12-13 04:51:15 +00:00
parent 27d3dfc453
commit 4e32f6b8de
1 changed files with 4 additions and 0 deletions
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4
nmigen/back/verilog.py
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@ -19,6 +19,7 @@ def convert(*args, **kwargs):
stderr=subprocess.PIPE, stderr=subprocess.PIPE,
encoding="utf-8") encoding="utf-8")
verilog_text, error = popen.communicate(""" verilog_text, error = popen.communicate("""
# Convert nMigen's RTLIL to readable Verilog.
read_ilang <<rtlil read_ilang <<rtlil
{} {}
rtlil rtlil
@ -27,6 +28,9 @@ proc_arst
proc_dff proc_dff
proc_clean proc_clean
write_verilog write_verilog
# Make sure there are no undriven wires in generated RTLIL.
proc
select -assert-none w:* i:* %a %d c:* %co* %a %d n:$* %d
""".format(il_text)) """.format(il_text))
if popen.returncode: if popen.returncode:
raise YosysError(error.strip()) raise YosysError(error.strip())