build.plat: use lib.io.*Buffer in default platform.
This commit is contained in:
Wanda
Catherine
parent
9bd536bbf9
commit
4e3550db43
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@ -12,6 +12,7 @@ from ..hdl import *
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from ..hdl._ir import IOBufferInstance, Design
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from ..hdl._xfrm import DomainLowerer
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from ..lib.cdc import ResetSynchronizer
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from ..lib import io
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from ..back import rtlil, verilog
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from .res import *
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from .run import *
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@ -138,8 +139,13 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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fragment._propagate_domains(self.create_missing_domain, platform=self)
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fragment = DomainLowerer()(fragment)
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def missing_domain_error(name):
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raise RuntimeError("Missing domain in pin fragment")
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def add_pin_fragment(pin, pin_fragment):
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pin_fragment = Fragment.get(pin_fragment, self)
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pin_fragment._propagate_domains(missing_domain_error)
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pin_fragment = DomainLowerer()(pin_fragment)
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fragment.add_subfragment(pin_fragment, name=f"pin_{pin.name}")
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for pin, port, attrs, invert in self.iter_single_ended_pins():
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@ -162,8 +168,7 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))
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ports = [(None, signal, None) for signal in self.iter_ports()]
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fragment = Design(fragment, ports, hierarchy=(name,))
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fragment = Design(fragment, [], hierarchy=(name,))
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return self.toolchain_prepare(fragment, name, **kwargs)
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@abstractmethod
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@ -201,63 +206,87 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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return value
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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self._check_feature("input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m.d.comb += pin.i.eq(self._invert_if(invert, port))
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Input, port)
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m.d.comb += pin.i.eq(buf.i)
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elif pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Input, port, i_domain="input")
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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elif pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Input, port, i_domain="input")
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m.d.comb += pin.i0.eq(buf.i[0])
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m.d.comb += pin.i1.eq(buf.i[1])
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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self._check_feature("output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m.d.comb += port.eq(self._invert_if(invert, pin.o))
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Output, port)
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m.d.comb += buf.o.eq(pin.o)
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elif pin.xdr == 1:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Output, port, o_domain="output")
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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elif pin.xdr == 2:
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Output, port, o_domain="output")
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m.d.comb += buf.o[0].eq(pin.o0)
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m.d.comb += buf.o[1].eq(pin.o1)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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if pin.dir == "oe":
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m.d.comb += buf.oe.eq(pin.oe)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.submodules += IOBufferInstance(
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port=port,
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o=self._invert_if(invert, pin.o),
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oe=pin.oe,
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)
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return m
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get_tristate = get_output
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i = Signal.like(pin.i)
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m.submodules += IOBufferInstance(
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port=port,
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i=i,
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o=self._invert_if(invert, pin.o),
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oe=pin.oe,
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)
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m.d.comb += pin.i.eq(self._invert_if(invert, i))
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if pin.xdr == 0:
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m.submodules.buf = buf = io.Buffer(io.Direction.Bidir, port)
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += buf.oe.eq(pin.oe)
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elif pin.xdr == 1:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.FFBuffer(io.Direction.Bidir, port, i_domain="input", o_domain="output")
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m.d.comb += pin.i.eq(buf.i)
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m.d.comb += buf.o.eq(pin.o)
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m.d.comb += buf.oe.eq(pin.oe)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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elif pin.xdr == 2:
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m.domains.input = cd_input = ClockDomain(reset_less=True)
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m.domains.output = cd_output = ClockDomain(reset_less=True)
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m.submodules.buf = buf = io.DDRBuffer(io.Direction.Bidir, port, i_domain="input", o_domain="output")
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m.d.comb += pin.i0.eq(buf.i[0])
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m.d.comb += pin.i1.eq(buf.i[1])
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m.d.comb += buf.o[0].eq(pin.o0)
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m.d.comb += buf.o[1].eq(pin.o1)
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m.d.comb += buf.oe.eq(pin.oe)
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m.d.comb += cd_input.clk.eq(pin.i_clk)
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m.d.comb += cd_output.clk.eq(pin.o_clk)
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return m
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def get_diff_input(self, pin, port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_output(self, pin, port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_tristate(self, pin, port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_input_output(self, pin, port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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get_diff_input = get_input
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get_diff_output = get_output
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get_diff_tristate = get_tristate
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get_diff_input_output = get_input_output
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class TemplatedPlatform(Platform):
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@ -18,6 +18,12 @@ class PortGroup:
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pass
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class PortMetadata:
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def __init__(self, name, attrs):
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self.name = name
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self.attrs = attrs
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class ResourceManager:
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def __init__(self, resources, connectors):
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self.resources = OrderedDict()
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@ -133,12 +139,21 @@ class ResourceManager:
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direction = phys.dir
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if isinstance(phys, Pins):
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phys_names = phys.names
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io = IOPort(len(phys), name="__".join(path) + "__io")
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io = IOPort(len(phys), name="__".join(path) + "__io", metadata=[
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PortMetadata(name, attrs)
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for name in phys.names
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])
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port = SingleEndedPort(io, invert=phys.invert, direction=direction)
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if isinstance(phys, DiffPairs):
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phys_names = []
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p = IOPort(len(phys), name="__".join(path) + "__p")
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n = IOPort(len(phys), name="__".join(path) + "__n")
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p = IOPort(len(phys), name="__".join(path) + "__p", metadata=[
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PortMetadata(name, attrs)
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for name in phys.p.names
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])
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n = IOPort(len(phys), name="__".join(path) + "__n", metadata=[
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PortMetadata(name, attrs)
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for name in phys.n.names
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])
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if not self.should_skip_port_component(None, attrs, "p"):
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phys_names += phys.p.names
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if not self.should_skip_port_component(None, attrs, "n"):
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