fhdl.ast: fix Switch with constant test.

nmigen/test/test_fhdl_dsl.py

@@ -263,6 +263,20 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
+    def test_Switch_const_test(self):
+        m = Module()
+        with m.Switch(1):
+            with m.Case(1):
+                m.d.comb += self.c1.eq(1)
+        m._flush()
+        self.assertRepr(m._statements, """
+        (
+            (switch (const 1'd1)
+                (case 1 (eq (sig c1) (const 1'd1)))
+            )
+        )
+        """)
+
     def test_Case_width_wrong(self):
         m = Module()
         with m.Switch(self.w1):