fhdl.ast: fix Switch with constant test.

This commit is contained in:
whitequark 2018-12-14 16:07:25 +00:00
parent a0d555a9fc
commit 50ba443f92
2 changed files with 16 additions and 2 deletions

View file

@ -678,9 +678,9 @@ class Switch(Statement):
self.cases = OrderedDict()
for key, stmts in cases.items():
if isinstance(key, (bool, int)):
key = "{:0{}b}".format(key, len(test))
key = "{:0{}b}".format(key, len(self.test))
elif isinstance(key, str):
assert len(key) == len(test)
assert len(key) == len(self.test)
else:
raise TypeError
if not isinstance(stmts, Iterable):

View file

@ -263,6 +263,20 @@ class DSLTestCase(FHDLTestCase):
)
""")
def test_Switch_const_test(self):
m = Module()
with m.Switch(1):
with m.Case(1):
m.d.comb += self.c1.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (const 1'd1)
(case 1 (eq (sig c1) (const 1'd1)))
)
)
""")
def test_Case_width_wrong(self):
m = Module()
with m.Switch(self.w1):