sim: group signal traces according to their function.
This commit is contained in:
Marek Materzok
Catherine
parent
89eae72a41
commit
51e0262710
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@ -212,17 +212,25 @@ class Simulator:
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file.close()
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raise ValueError("Cannot start writing waveforms after advancing simulation time")
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for trace in traces:
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if isinstance(trace, ValueLike):
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trace_cast = Value.cast(trace)
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def traverse_traces(traces):
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if isinstance(traces, ValueLike):
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trace_cast = Value.cast(traces)
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if isinstance(trace_cast, MemoryData._Row):
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continue
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return
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for trace_signal in trace_cast._rhs_signals():
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if trace_signal.name == "":
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if trace_signal is trace:
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if trace_signal is traces:
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raise TypeError("Cannot trace signal with private name")
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else:
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raise TypeError(f"Cannot trace signal with private name (within {trace!r})")
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raise TypeError(f"Cannot trace signal with private name (within {traces!r})")
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elif isinstance(traces, (list, tuple)):
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for trace in traces:
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traverse_traces(trace)
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elif isinstance(traces, dict):
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for trace in traces.values():
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traverse_traces(trace)
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traverse_traces(traces)
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return self._engine.write_vcd(vcd_file=vcd_file, gtkw_file=gtkw_file,
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traces=traces, fs_per_delta=fs_per_delta)
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@ -5,7 +5,9 @@ import os.path
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import enum as py_enum
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from ..hdl import *
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from ..hdl._mem import MemoryInstance
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from ..hdl._ast import SignalDict
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from ..lib import data, wiring
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from ._base import *
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from ._async import *
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from ._pyeval import eval_format, eval_value, eval_assign
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@ -49,7 +51,7 @@ class _VCDWriter:
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self.gtkw_file = gtkw_file
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self.gtkw_save = gtkw_file and vcd.gtkw.GTKWSave(self.gtkw_file)
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self.traces = []
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self.traces = traces
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signal_names = SignalDict()
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memories = {}
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@ -64,9 +66,9 @@ class _VCDWriter:
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trace_names = SignalDict()
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assigned_names = set()
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for trace in traces:
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if isinstance(trace, ValueLike):
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trace = Value.cast(trace)
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def traverse_traces(traces):
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if isinstance(traces, ValueLike):
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trace = Value.cast(traces)
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if isinstance(trace, MemoryData._Row):
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memory = trace._memory
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if not memory in memories:
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@ -77,7 +79,6 @@ class _VCDWriter:
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assert name not in assigned_names
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memories[memory] = ("bench", name)
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assigned_names.add(name)
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self.traces.append(trace)
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else:
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for trace_signal in trace._rhs_signals():
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if trace_signal not in signal_names:
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@ -88,19 +89,27 @@ class _VCDWriter:
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assert name not in assigned_names
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trace_names[trace_signal] = {("bench", name)}
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assigned_names.add(name)
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self.traces.append(trace_signal)
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elif isinstance(trace, MemoryData):
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if not trace in memories:
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if trace.name not in assigned_names:
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name = trace.name
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elif isinstance(traces, MemoryData):
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if not traces in memories:
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if traces.name not in assigned_names:
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name = traces.name
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else:
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name = f"{trace.name}${len(assigned_names)}"
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name = f"{traces.name}${len(assigned_names)}"
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assert name not in assigned_names
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memories[trace] = ("bench", name)
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memories[traces] = ("bench", name)
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assigned_names.add(name)
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self.traces.append(trace)
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elif hasattr(traces, "signature") and isinstance(traces.signature, wiring.Signature):
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for name in traces.signature.members:
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traverse_traces(getattr(traces, name))
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elif isinstance(traces, list) or isinstance(traces, tuple):
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for trace in traces:
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traverse_traces(trace)
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elif isinstance(traces, dict):
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for trace in traces.values():
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traverse_traces(trace)
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else:
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raise TypeError(f"{trace!r} is not a traceable object")
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raise TypeError(f"{traces!r} is not a traceable object")
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traverse_traces(traces)
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if self.vcd_writer is None:
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return
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@ -277,19 +286,40 @@ class _VCDWriter:
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self.gtkw_save.dumpfile_size(self.vcd_file.tell())
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self.gtkw_save.treeopen("top")
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for trace in self.traces:
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if isinstance(trace, Signal):
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for name in self.gtkw_signal_names[trace]:
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def traverse_traces(traces):
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if isinstance(traces, Signal):
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for name in self.gtkw_signal_names[traces]:
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self.gtkw_save.trace(name)
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elif isinstance(trace, MemoryData):
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for row_names in self.gtkw_memory_names[trace]:
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elif isinstance(traces, data.View):
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with self.gtkw_save.group("view"):
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trace = Value.cast(traces)
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for trace_signal in trace._rhs_signals():
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for name in self.gtkw_signal_names[trace_signal]:
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self.gtkw_save.trace(name)
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elif isinstance(traces, ValueLike):
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traverse_traces(Value.cast(traces))
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elif isinstance(traces, MemoryData):
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for row_names in self.gtkw_memory_names[traces]:
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for name in row_names:
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self.gtkw_save.trace(name)
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elif isinstance(trace, MemoryData._Row):
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for name in self.gtkw_memory_names[trace._memory][trace._index]:
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elif isinstance(traces, MemoryData._Row):
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for name in self.gtkw_memory_names[traces._memory][traces._index]:
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self.gtkw_save.trace(name)
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elif hasattr(traces, "signature") and isinstance(traces.signature, wiring.Signature):
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with self.gtkw_save.group("interface"):
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for _, _, member in traces.signature.flatten(traces):
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traverse_traces(member)
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elif isinstance(traces, list) or isinstance(traces, tuple):
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for trace in traces:
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traverse_traces(trace)
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elif isinstance(traces, dict):
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for name, trace in traces.items():
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with self.gtkw_save.group(name):
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traverse_traces(trace)
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else:
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assert False # :nocov:
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traverse_traces(self.traces)
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if self.close_vcd:
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self.vcd_file.close()
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@ -16,7 +16,7 @@ from amaranth.hdl._ir import *
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from amaranth.sim import *
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from amaranth.sim._pyeval import eval_format
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from amaranth.lib.memory import Memory
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from amaranth.lib import enum, data
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from amaranth.lib import enum, data, wiring
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from .utils import *
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from amaranth._utils import _ignore_deprecated
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@ -1393,6 +1393,49 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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sim.add_testbench(testbench)
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class SimulatorTracesTestCase(FHDLTestCase):
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def assertDef(self, traces, flat_traces):
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frag = Fragment()
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def process():
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yield Delay(1e-6)
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sim = Simulator(frag)
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd", "test.gtkw", traces=traces):
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sim.run()
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def test_signal(self):
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a = Signal()
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self.assertDef(a, [a])
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def test_list(self):
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a = Signal()
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self.assertDef([a], [a])
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def test_tuple(self):
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a = Signal()
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self.assertDef((a,), [a])
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def test_dict(self):
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a = Signal()
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self.assertDef({"a": a}, [a])
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def test_struct_view(self):
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a = Signal(data.StructLayout({"a": 1, "b": 3}))
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self.assertDef(a, [a])
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def test_interface(self):
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sig = wiring.Signature({
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"a": wiring.In(1),
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"b": wiring.Out(3),
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"c": wiring.Out(2).array(4),
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"d": wiring.In(wiring.Signature({"e": wiring.In(5)}))
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})
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a = sig.create()
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self.assertDef(a, [a])
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class SimulatorRegressionTestCase(FHDLTestCase):
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def test_bug_325(self):
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dut = Module()
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