vendor.xilinx_spartan_3_6: override reset synchronizer.
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c16f5ecf34
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51f03bb509
12
nmigen/vendor/xilinx_spartan_3_6.py
vendored
12
nmigen/vendor/xilinx_spartan_3_6.py
vendored
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@ -419,6 +419,18 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
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m.d.comb += ff_sync.o.eq(multireg._stages[-1])
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return m
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def get_reset_sync(self, resetsync):
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m = Module()
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m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
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for i, o in zip((0, *resetsync._stages), resetsync._stages):
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o.attrs["ASYNC_REG"] = "TRUE"
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m.d.reset_sync += o.eq(i)
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m.d.comb += [
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ClockSignal("reset_sync").eq(ClockSignal(resetsync._domain)),
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ResetSignal("reset_sync").eq(resetsync.arst),
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ResetSignal(resetsync._domain).eq(resetsync._stages[-1])
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]
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return m
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XilinxSpartan3APlatform = XilinxSpartan3Or6Platform
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XilinxSpartan6Platform = XilinxSpartan3Or6Platform
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