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vendor.xilinx_spartan_3_6: override reset synchronizer.

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Darrell Harmon 2019-09-23 10:28:15 -06:00 committed by whitequark
parent c16f5ecf34
commit 51f03bb509
1 changed files with 12 additions and 0 deletions
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12
nmigen/vendor/xilinx_spartan_3_6.py vendored
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@ -419,6 +419,18 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
m.d.comb += ff_sync.o.eq(multireg._stages[-1]) m.d.comb += ff_sync.o.eq(multireg._stages[-1])
return m return m
def get_reset_sync(self, resetsync):
m = Module()
m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
for i, o in zip((0, *resetsync._stages), resetsync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
m.d.reset_sync += o.eq(i)
m.d.comb += [
ClockSignal("reset_sync").eq(ClockSignal(resetsync._domain)),
ResetSignal("reset_sync").eq(resetsync.arst),
ResetSignal(resetsync._domain).eq(resetsync._stages[-1])
]
return m
XilinxSpartan3APlatform = XilinxSpartan3Or6Platform XilinxSpartan3APlatform = XilinxSpartan3Or6Platform
XilinxSpartan6Platform = XilinxSpartan3Or6Platform XilinxSpartan6Platform = XilinxSpartan3Or6Platform