compat: fix confusing naming for memory port address signal.

2018-12-22 00:53:05 +00:00 · 2018-12-22 00:53:05 +00:00 · 5361b4c22b
parent f6772759c8
commit 5361b4c22b
1 changed files with 1 additions and 0 deletions
--- a/nmigen/compat/fhdl/specials.py
+++ b/nmigen/compat/fhdl/specials.py
@ -64,6 +64,7 @@ class CompatMemory(NativeMemory):
            we_granularity = None
        assert mode != NO_CHANGE
        rdport = self.read_port(synchronous=not async_read, transparent=mode == WRITE_FIRST)
+        rdport.addr.name = "{}_addr".format(self.name)
        adr = rdport.addr
        dat_r = rdport.data
        if write_capable: