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sim.pysim: use "bench" as a top level root for testbench signals.

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Fixes #561.
This commit is contained in:
Irides 2021-12-15 19:47:48 -06:00 • committed by Catherine
parent 810c19dde4
commit 538c14116c
3 changed files with 4 additions and 3 deletions
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4
amaranth/sim/pysim.py
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@ -19,7 +19,7 @@ class _NameExtractor:
def __init__(self):
self.names = SignalDict()
def __call__(self, fragment, *, hierarchy=("top",)):
def __call__(self, fragment, *, hierarchy=("bench", "top",)):
def add_signal_name(signal):
hierarchical_signal_name = (*hierarchy, signal.name)
if signal not in self.names:
@ -74,7 +74,7 @@ class _VCDWriter:
trace_names = SignalDict()
for trace in traces:
if trace not in signal_names:
trace_names[trace] = {("top", trace.name)}
trace_names[trace] = {('bench', trace.name)}
self.traces.append(trace)
if self.vcd_writer is None: