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sim.pysim: use "bench" as a top level root for testbench signals.

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Fixes #561.
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Irides 2021-12-15 19:47:48 -06:00 • committed by Catherine
parent 810c19dde4
commit 538c14116c
3 changed files with 4 additions and 3 deletions
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docs/changes.rst
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@ -74,6 +74,7 @@ Toolchain changes
* Added: :meth:`build.BuildPlan.execute_remote_ssh`.
* Deprecated: :class:`test.utils.FHDLTestCase`, with no replacement.
* Deprecated: :func:`back.rtlil.convert()` and :func:`back.verilog.convert()` without an explicit `ports=` argument.
* Changed: VCD output now uses a top-level "bench" module that contains testbench only signals.
Platform integration changes