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sim.pysim: use "bench" as a top level root for testbench signals.

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Fixes #561.
This commit is contained in:
Irides 2021-12-15 19:47:48 -06:00 • committed by Catherine
parent 810c19dde4
commit 538c14116c
3 changed files with 4 additions and 3 deletions
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2
tests/test_sim.py
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@ -849,7 +849,7 @@ class SimulatorRegressionTestCase(FHDLTestCase):
pass
sim = Simulator(dut)
with self.assertRaisesRegex(NameError,
r"^Signal 'top\.name with space_state' contains a whitespace character$"):
r"^Signal 'bench\.top\.name with space_state' contains a whitespace character$"):
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
sim.run()