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sim.pysim: use "bench" as a top level root for testbench signals.

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Fixes #561.
This commit is contained in:
Irides 2021-12-15 19:47:48 -06:00 committed by Catherine
parent 810c19dde4
commit 538c14116c
3 changed files with 4 additions and 3 deletions
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4
amaranth/sim/pysim.py
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@ -19,7 +19,7 @@ class _NameExtractor:
def __init__(self): def __init__(self):
self.names = SignalDict() self.names = SignalDict()
def __call__(self, fragment, *, hierarchy=("top",)): def __call__(self, fragment, *, hierarchy=("bench", "top",)):
def add_signal_name(signal): def add_signal_name(signal):
hierarchical_signal_name = (*hierarchy, signal.name) hierarchical_signal_name = (*hierarchy, signal.name)
if signal not in self.names: if signal not in self.names:
@ -74,7 +74,7 @@ class _VCDWriter:
trace_names = SignalDict() trace_names = SignalDict()
for trace in traces: for trace in traces:
if trace not in signal_names: if trace not in signal_names:
trace_names[trace] = {("top", trace.name)} trace_names[trace] = {('bench', trace.name)}
self.traces.append(trace) self.traces.append(trace)
if self.vcd_writer is None: if self.vcd_writer is None:

1
docs/changes.rst
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@ -74,6 +74,7 @@ Toolchain changes
* Added: :meth:`build.BuildPlan.execute_remote_ssh`. * Added: :meth:`build.BuildPlan.execute_remote_ssh`.
* Deprecated: :class:`test.utils.FHDLTestCase`, with no replacement. * Deprecated: :class:`test.utils.FHDLTestCase`, with no replacement.
* Deprecated: :func:`back.rtlil.convert()` and :func:`back.verilog.convert()` without an explicit `ports=` argument. * Deprecated: :func:`back.rtlil.convert()` and :func:`back.verilog.convert()` without an explicit `ports=` argument.
* Changed: VCD output now uses a top-level "bench" module that contains testbench only signals.
Platform integration changes Platform integration changes

2
tests/test_sim.py
View file

@ -849,7 +849,7 @@ class SimulatorRegressionTestCase(FHDLTestCase):
pass pass
sim = Simulator(dut) sim = Simulator(dut)
with self.assertRaisesRegex(NameError, with self.assertRaisesRegex(NameError,
r"^Signal 'top\.name with space_state' contains a whitespace character$"): r"^Signal 'bench\.top\.name with space_state' contains a whitespace character$"):
with open(os.path.devnull, "w") as f: with open(os.path.devnull, "w") as f:
with sim.write_vcd(f): with sim.write_vcd(f):
sim.run() sim.run()