build.plat: strip internal attributes from Verilog output.

Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.

This still leaves the (*init*) attribute. See #220 for details.

nmigen/vendor/lattice_ecp5.py

@@ -101,7 +101,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -182,7 +182,11 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             prj_project new -name {{name}} -impl impl -impl_dir top_impl \

nmigen/vendor/lattice_ice40.py

@@ -105,7 +105,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
-            {{emit_design("rtlil")}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
@@ -196,7 +196,11 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}_lse.prj": r"""
             # {{autogenerated}}

nmigen/vendor/xilinx_7series.py

@@ -63,7 +63,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.tcl": r"""
             # {{autogenerated}}

nmigen/vendor/xilinx_spartan_3_6.py

@@ -93,7 +93,11 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         """,
         "{{name}}.v": r"""
             /* {{autogenerated}} */
-            {{emit_design("verilog")}}
+            {{emit_verilog()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}