compat: provide Memory shim.

This commit is contained in:
whitequark 2018-12-21 13:15:52 +00:00
parent fa2af27bb0
commit 568d3c5b7d
2 changed files with 86 additions and 5 deletions

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@ -54,11 +54,11 @@ Compatibility summary
- () `Tristate` ?
- (+) `TSTriple``.lib.io.TSTriple`, `bits_sign=``shape=`
- () `Instance` ?
- () `Memory` id
- () `.get_port` **obs**`.read_port()` + `.write_port()`
- () `_MemoryPort` **obs**
- (+) `Memory` id
- (+) `.get_port` **obs**`.read_port()` + `.write_port()`
- (+) `_MemoryPort` **obs**
<br>Note: nMigen separates read and write ports.
- () `READ_FIRST`/`WRITE_FIRST` **obs**
- (+) `READ_FIRST`/`WRITE_FIRST` **obs**
<br>Note: `READ_FIRST` corresponds to `mem.read_port(transparent=False)`, and `WRITE_FIRST` to `mem.read_port(transparent=True)`.
- (-) `NO_CHANGE` **brk**
<br>Note: in designs using `NO_CHANGE`, repalce it with an asynchronous read port and logic implementing required semantics explicitly.