hdl._nir, back.rtlil: use Format.* to emit enum attributes and wires for fields.
This commit is contained in:
Wanda
Catherine
parent
4cb2dde25f
commit
580706fafd
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@ -3,6 +3,7 @@ from contextlib import contextmanager
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import io
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from ..utils import bits_for
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from .._utils import to_binary
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from ..lib import wiring
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from ..hdl import _repr, _ast, _ir, _nir
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@ -421,6 +422,7 @@ class ModuleEmitter:
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self.emit_cell_wires()
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self.emit_submodule_wires()
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self.emit_connects()
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self.emit_signal_fields()
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self.emit_submodules()
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self.emit_cells()
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@ -491,12 +493,12 @@ class ModuleEmitter:
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attrs.update(signal.attrs)
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self.value_src_loc[value] = signal.src_loc
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for repr in signal._value_repr:
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if repr.path == () and isinstance(repr.format, _repr.FormatEnum):
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enum = repr.format.enum
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attrs["enum_base_type"] = enum.__name__
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for enum_value in enum:
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attrs["enum_value_{:0{}b}".format(enum_value.value, len(signal))] = enum_value.name
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field = self.netlist.signal_fields[signal][()]
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if field.enum_name is not None:
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attrs["enum_base_type"] = field.enum_name
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if field.enum_variants is not None:
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for var_val, var_name in field.enum_variants.items():
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attrs["enum_value_" + to_binary(var_val, len(signal))] = var_name
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if name in self.module.ports:
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port_value, _flow = self.module.ports[name]
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@ -666,6 +668,30 @@ class ModuleEmitter:
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if name not in self.driven_sigports:
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self.builder.connect(wire.name, self.sigspec(value))
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def emit_signal_fields(self):
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for signal, name in self.module.signal_names.items():
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fields = self.netlist.signal_fields[signal]
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for path, field in fields.items():
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if path == ():
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continue
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name_parts = [name]
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for component in path:
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if isinstance(component, str):
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name_parts.append(f".{component}")
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elif isinstance(component, int):
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name_parts.append(f"[{component}]")
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else:
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assert False # :nocov:
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attrs = {}
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if field.enum_name is not None:
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attrs["enum_base_type"] = field.enum_name
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if field.enum_variants is not None:
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for var_val, var_name in field.enum_variants.items():
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attrs["enum_value_" + to_binary(var_val, len(field.value))] = var_name
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wire = self.builder.wire(width=len(field.value), signed=field.signed, attrs=attrs,
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name="".join(name_parts), src_loc=signal.src_loc)
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self.builder.connect(wire.name, self.sigspec(field.value))
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def emit_submodules(self):
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for submodule_idx in self.module.submodules:
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submodule = self.netlist.modules[submodule_idx]
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@ -2095,6 +2095,11 @@ class Signal(Value, DUID, metaclass=_SignalMeta):
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self._attrs = OrderedDict(() if attrs is None else attrs)
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if isinstance(orig_shape, ShapeCastable):
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self._format = orig_shape.format(orig_shape(self), "")
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else:
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self._format = Format("{}", self)
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if decoder is not None:
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# The value representation is specified explicitly. Since we do not expose `hdl._repr`,
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# this is the only way to add a custom filter to the signal right now.
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@ -690,7 +690,7 @@ class NetlistDriver:
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class NetlistEmitter:
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def __init__(self, netlist: _nir.Netlist, design, *, all_undef_to_ff=False):
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def __init__(self, netlist: _nir.Netlist, design: Design, *, all_undef_to_ff=False):
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self.netlist = netlist
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self.design = design
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self.all_undef_to_ff = all_undef_to_ff
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@ -776,7 +776,7 @@ class NetlistEmitter:
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def emit_operator(self, module_idx: int, operator: str, *inputs: _nir.Value, src_loc):
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op = _nir.Operator(module_idx, operator=operator, inputs=inputs, src_loc=src_loc)
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return self.netlist.add_value_cell(op.width, op)
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def emit_matches(self, module_idx: int, value: _nir.Value, patterns, *, src_loc):
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key = module_idx, value, patterns, src_loc
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try:
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@ -1334,6 +1334,42 @@ class NetlistEmitter:
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else:
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raise ValueError(f"Invalid port direction {dir!r}")
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def emit_signal_fields(self):
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for signal, fragment in self.design.signal_lca.items():
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module_idx = self.fragment_module_idx[fragment]
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fields = {}
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def emit_format(path, fmt):
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if isinstance(fmt, _ast.Format):
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specs = [
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chunk[0]
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for chunk in fmt._chunks
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if not isinstance(chunk, str)
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]
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if len(specs) != 1:
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return
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val, signed = self.emit_rhs(module_idx, specs[0])
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fields[path] = _nir.SignalField(val, signed=signed)
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elif isinstance(fmt, _ast.Format.Enum):
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val, signed = self.emit_rhs(module_idx, fmt._value)
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fields[path] = _nir.SignalField(val, signed=signed,
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enum_name=fmt._name,
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enum_variants=fmt._variants)
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elif isinstance(fmt, _ast.Format.Struct):
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val, signed = self.emit_rhs(module_idx, fmt._value)
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fields[path] = _nir.SignalField(val, signed=signed)
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for name, subfmt in fmt._fields.items():
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emit_format(path + (name,), subfmt)
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elif isinstance(fmt, _ast.Format.Array):
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val, signed = self.emit_rhs(module_idx, fmt._value)
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fields[path] = _nir.SignalField(val, signed=signed)
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for idx, subfmt in enumerate(fmt._fields):
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emit_format(path + (idx,), subfmt)
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emit_format((), signal._format)
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val, signed = self.emit_rhs(module_idx, signal)
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if () not in fields or fields[()].value != val:
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fields[()] = _nir.SignalField(val, signed=signed)
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self.netlist.signal_fields[signal] = fields
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def emit_drivers(self):
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for driver in self.drivers.values():
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if (driver.domain is not None and
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@ -1452,6 +1488,7 @@ class NetlistEmitter:
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for subfragment, _name, sub_src_loc in fragment.subfragments:
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self.emit_fragment(subfragment, module_idx, cell_src_loc=sub_src_loc)
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if parent_module_idx is None:
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self.emit_signal_fields()
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self.emit_drivers()
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self.emit_top_ports(fragment)
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if self.all_undef_to_ff:
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@ -289,6 +289,22 @@ class Format:
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chunk.value = netlist.resolve_value(chunk.value)
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class SignalField:
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"""Describes a single field of a signal."""
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def __init__(self, value, *, signed, enum_name=None, enum_variants=None):
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self.value = Value(value)
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self.signed = bool(signed)
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self.enum_name = enum_name
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self.enum_variants = enum_variants
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def __eq__(self, other):
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return (type(self) is type(other) and
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self.value == other.value and
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self.signed == other.signed and
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self.enum_name == other.enum_name and
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self.enum_variants == other.enum_variants)
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class Netlist:
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"""A fine netlist. Consists of:
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@ -321,6 +337,7 @@ class Netlist:
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connections : dict of (negative) int to int
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io_ports : list of ``IOPort``
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signals : dict of Signal to ``Value``
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signal_fields: dict of Signal to dict of tuple[str | int] to SignalField
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last_late_net: int
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"""
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def __init__(self):
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@ -329,6 +346,7 @@ class Netlist:
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self.connections: dict[Net, Net] = {}
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self.io_ports: list[_ast.IOPort] = []
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self.signals = SignalDict()
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self.signal_fields = SignalDict()
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self.last_late_net = 0
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def resolve_net(self, net: Net):
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@ -345,6 +363,9 @@ class Netlist:
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cell.resolve_nets(self)
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for sig in self.signals:
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self.signals[sig] = self.resolve_value(self.signals[sig])
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for fields in self.signal_fields.values():
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for field in fields.values():
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field.value = self.resolve_value(field.value)
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def __repr__(self):
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result = ["("]
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@ -4,7 +4,7 @@ import re
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from amaranth.back import rtlil
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from amaranth.hdl import *
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from amaranth.hdl._ast import *
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from amaranth.lib import memory, wiring
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from amaranth.lib import memory, wiring, data, enum
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from .utils import *
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@ -2010,6 +2010,67 @@ class PrintTestCase(RTLILTestCase):
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""")
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class DetailTestCase(RTLILTestCase):
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def test_enum(self):
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class MyEnum(enum.Enum, shape=unsigned(2)):
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A = 0
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B = 1
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C = 2
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sig = Signal(MyEnum)
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m = Module()
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m.d.comb += sig.eq(MyEnum.A)
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self.assertRTLIL(m, [sig.as_value()], R"""
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attribute \generator "Amaranth"
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attribute \top 1
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module \top
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attribute \enum_base_type "MyEnum"
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attribute \enum_value_00 "A"
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attribute \enum_value_01 "B"
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attribute \enum_value_10 "C"
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wire width 2 output 0 \sig
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connect \sig 2'00
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end
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""")
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def test_struct(self):
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class MyEnum(enum.Enum, shape=unsigned(2)):
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A = 0
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B = 1
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C = 2
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class Meow(data.Struct):
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a: MyEnum
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b: 3
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c: signed(4)
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d: data.ArrayLayout(2, 2)
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sig = Signal(Meow)
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m = Module()
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self.assertRTLIL(m, [sig.as_value()], R"""
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attribute \generator "Amaranth"
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attribute \top 1
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module \top
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wire width 13 input 0 \sig
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attribute \enum_base_type "MyEnum"
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attribute \enum_value_00 "A"
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attribute \enum_value_01 "B"
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attribute \enum_value_10 "C"
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wire width 2 \sig.a
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wire width 3 \sig.b
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wire width 4 signed \sig.c
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wire width 4 \sig.d
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wire width 2 \sig.d[0]
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wire width 2 \sig.d[1]
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connect \sig.a \sig [1:0]
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connect \sig.b \sig [4:2]
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connect \sig.c \sig [8:5]
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connect \sig.d \sig [12:9]
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connect \sig.d[0] \sig [10:9]
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connect \sig.d[1] \sig [12:11]
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end
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""")
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class ComponentTestCase(RTLILTestCase):
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def test_component(self):
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class MyComponent(wiring.Component):
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@ -7,6 +7,9 @@ from amaranth.hdl._cd import *
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from amaranth.hdl._dsl import *
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from amaranth.hdl._ir import *
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from amaranth.hdl._mem import *
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from amaranth.hdl._nir import SignalField
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from amaranth.lib import enum, data
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from .utils import *
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@ -3501,3 +3504,41 @@ class UndrivenTestCase(FHDLTestCase):
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(cell 3 0 (flipflop 3.0:5 10 pos 0 0))
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)
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""")
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class FieldsTestCase(FHDLTestCase):
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def test_fields(self):
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class MyEnum(enum.Enum, shape=unsigned(2)):
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A = 0
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B = 1
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C = 2
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l = data.StructLayout({"a": MyEnum, "b": signed(3)})
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s1 = Signal(l)
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s2 = Signal(MyEnum)
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s3 = Signal(signed(3))
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s4 = Signal(unsigned(4))
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nl = build_netlist(Fragment.get(Module(), None), [
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s1.as_value(), s2.as_value(), s3, s4,
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])
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self.assertEqual(nl.signal_fields[s1.as_value()], {
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(): SignalField(nl.signals[s1.as_value()], signed=False),
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('a',): SignalField(nl.signals[s1.as_value()][0:2], signed=False, enum_name="MyEnum", enum_variants={
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0: "A",
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1: "B",
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2: "C",
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}),
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('b',): SignalField(nl.signals[s1.as_value()][2:5], signed=True)
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})
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self.assertEqual(nl.signal_fields[s2.as_value()], {
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(): SignalField(nl.signals[s2.as_value()], signed=False, enum_name="MyEnum", enum_variants={
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0: "A",
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1: "B",
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2: "C",
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}),
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})
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self.assertEqual(nl.signal_fields[s3], {
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(): SignalField(nl.signals[s3], signed=True),
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})
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self.assertEqual(nl.signal_fields[s4], {
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(): SignalField(nl.signals[s4], signed=False),
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})
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@ -647,6 +647,9 @@ class ViewTestCase(FHDLTestCase):
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def from_bits(self, bits):
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return bits
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def format(self, value, spec):
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return Format("")
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v = Signal(data.StructLayout({
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"f": WrongCastable()
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}))
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