hdl._nir, back.rtlil: use Format.* to emit enum attributes and wires for fields.

tests/test_back_rtlil.py

@@ -4,7 +4,7 @@ import re
 from amaranth.back import rtlil
 from amaranth.hdl import *
 from amaranth.hdl._ast import *
-from amaranth.lib import memory, wiring
+from amaranth.lib import memory, wiring, data, enum
 
 from .utils import *
 
@@ -2010,6 +2010,67 @@ class PrintTestCase(RTLILTestCase):
         """)
 
 
+class DetailTestCase(RTLILTestCase):
+    def test_enum(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+
+        sig = Signal(MyEnum)
+        m = Module()
+        m.d.comb += sig.eq(MyEnum.A)
+        self.assertRTLIL(m, [sig.as_value()], R"""
+        attribute \generator "Amaranth"
+        attribute \top 1
+        module \top
+            attribute \enum_base_type "MyEnum"
+            attribute \enum_value_00 "A"
+            attribute \enum_value_01 "B"
+            attribute \enum_value_10 "C"
+            wire width 2 output 0 \sig
+            connect \sig 2'00
+        end
+        """)
+
+    def test_struct(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+
+        class Meow(data.Struct):
+            a: MyEnum
+            b: 3
+            c: signed(4)
+            d: data.ArrayLayout(2, 2)
+
+        sig = Signal(Meow)
+        m = Module()
+        self.assertRTLIL(m, [sig.as_value()], R"""
+        attribute \generator "Amaranth"
+        attribute \top 1
+        module \top
+            wire width 13 input 0 \sig
+            attribute \enum_base_type "MyEnum"
+            attribute \enum_value_00 "A"
+            attribute \enum_value_01 "B"
+            attribute \enum_value_10 "C"
+            wire width 2 \sig.a
+            wire width 3 \sig.b
+            wire width 4 signed \sig.c
+            wire width 4 \sig.d
+            wire width 2 \sig.d[0]
+            wire width 2 \sig.d[1]
+            connect \sig.a \sig [1:0]
+            connect \sig.b \sig [4:2]
+            connect \sig.c \sig [8:5]
+            connect \sig.d \sig [12:9]
+            connect \sig.d[0] \sig [10:9]
+            connect \sig.d[1] \sig [12:11]
+        end
+        """)
+
 class ComponentTestCase(RTLILTestCase):
     def test_component(self):
         class MyComponent(wiring.Component):

tests/test_hdl_ir.py

@@ -7,6 +7,9 @@ from amaranth.hdl._cd import *
 from amaranth.hdl._dsl import *
 from amaranth.hdl._ir import *
 from amaranth.hdl._mem import *
+from amaranth.hdl._nir import SignalField
+
+from amaranth.lib import enum, data
 
 from .utils import *
 
@@ -3501,3 +3504,41 @@ class UndrivenTestCase(FHDLTestCase):
             (cell 3 0 (flipflop 3.0:5 10 pos 0 0))
         )
         """)
+
+
+class FieldsTestCase(FHDLTestCase):
+    def test_fields(self):
+        class MyEnum(enum.Enum, shape=unsigned(2)):
+            A = 0
+            B = 1
+            C = 2
+        l = data.StructLayout({"a": MyEnum, "b": signed(3)})
+        s1 = Signal(l)
+        s2 = Signal(MyEnum)
+        s3 = Signal(signed(3))
+        s4 = Signal(unsigned(4))
+        nl = build_netlist(Fragment.get(Module(), None), [
+            s1.as_value(), s2.as_value(), s3, s4,
+        ])
+        self.assertEqual(nl.signal_fields[s1.as_value()], {
+            (): SignalField(nl.signals[s1.as_value()], signed=False),
+            ('a',): SignalField(nl.signals[s1.as_value()][0:2], signed=False, enum_name="MyEnum", enum_variants={
+                0: "A",
+                1: "B",
+                2: "C",
+            }),
+            ('b',): SignalField(nl.signals[s1.as_value()][2:5], signed=True)
+        })
+        self.assertEqual(nl.signal_fields[s2.as_value()], {
+            (): SignalField(nl.signals[s2.as_value()], signed=False, enum_name="MyEnum", enum_variants={
+                0: "A",
+                1: "B",
+                2: "C",
+            }),
+        })
+        self.assertEqual(nl.signal_fields[s3], {
+            (): SignalField(nl.signals[s3], signed=True),
+        })
+        self.assertEqual(nl.signal_fields[s4], {
+            (): SignalField(nl.signals[s4], signed=False),
+        })

tests/test_lib_data.py

@@ -647,6 +647,9 @@ class ViewTestCase(FHDLTestCase):
             def from_bits(self, bits):
                 return bits
 
+            def format(self, value, spec):
+                return Format("")
+
         v = Signal(data.StructLayout({
             "f": WrongCastable()
         }))