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hdl.ir: rework named port handling for Instances.

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The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
This commit is contained in:
whitequark 2019-04-22 07:46:47 +00:00
parent aed2062101
commit 585514e6ed
4 changed files with 26 additions and 29 deletions
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15
nmigen/test/test_hdl_ir.py
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@ -531,11 +531,14 @@ class InstanceTestCase(FHDLTestCase):
self.rst = Signal()
self.stb = Signal()
self.pins = Signal(8)
self.datal = Signal(4)
self.datah = Signal(4)
self.inst = Instance("cpu",
p_RESET=0x1234,
i_clk=ClockSignal(),
i_rst=self.rst,
o_stb=self.stb,
o_data=Cat(self.datal, self.datah),
io_pins=self.pins
)
@ -544,22 +547,18 @@ class InstanceTestCase(FHDLTestCase):
f = self.inst
self.assertEqual(f.type, "cpu")
self.assertEqual(f.parameters, OrderedDict([("RESET", 0x1234)]))
self.assertEqual(list(f.named_ports.keys()), ["clk", "rst", "stb", "pins"])
self.assertEqual(f.ports, SignalDict([
(self.stb, "o"),
(self.pins, "io"),
]))
self.assertEqual(list(f.named_ports.keys()), ["clk", "rst", "stb", "data", "pins"])
self.assertEqual(f.ports, SignalDict([]))
def test_prepare(self):
self.setUp_cpu()
f = self.inst.prepare()
clk = f.domains["sync"].clk
self.assertEqual(f.type, "cpu")
self.assertEqual(f.parameters, OrderedDict([("RESET", 0x1234)]))
self.assertEqual(list(f.named_ports.keys()), ["clk", "rst", "stb", "pins"])
self.assertEqual(f.ports, SignalDict([
(clk, "i"),
(self.rst, "i"),
(self.stb, "o"),
(self.datal, "o"),
(self.datah, "o"),
(self.pins, "io"),
]))