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xilinx_{7series,ultrascale}: run report_methodology.

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This can expose important timing issues, such as #301.
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whitequark 2020-02-06 19:38:21 +00:00
parent 27b47faf16
commit 5888f29c1f
2 changed files with 4 additions and 0 deletions
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2
nmigen/vendor/xilinx_7series.py vendored
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@ -38,6 +38,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
* ``{{name}}_clock_utilization.rpt``: Vivado report.
* ``{{name}}_route_status.rpt``: Vivado report.
* ``{{name}}_drc.rpt``: Vivado report.
* ``{{name}}_methodology.rpt``: Vivado report.
* ``{{name}}_timing.rpt``: Vivado report.
* ``{{name}}_power.rpt``: Vivado report.
* ``{{name}}_route.dcp``: Vivado design checkpoint.
@ -116,6 +117,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
write_checkpoint -force {{name}}_route.dcp
report_route_status -file {{name}}_route_status.rpt
report_drc -file {{name}}_drc.rpt
report_methodology -file {{name}}_methodology.rpt
report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
report_power -file {{name}}_power.rpt
{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}

2
nmigen/vendor/xilinx_ultrascale.py vendored
View file

@ -38,6 +38,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
* ``{{name}}_clock_utilization.rpt``: Vivado report.
* ``{{name}}_route_status.rpt``: Vivado report.
* ``{{name}}_drc.rpt``: Vivado report.
* ``{{name}}_methodology.rpt``: Vivado report.
* ``{{name}}_timing.rpt``: Vivado report.
* ``{{name}}_power.rpt``: Vivado report.
* ``{{name}}_route.dcp``: Vivado design checkpoint.
@ -116,6 +117,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
write_checkpoint -force {{name}}_route.dcp
report_route_status -file {{name}}_route_status.rpt
report_drc -file {{name}}_drc.rpt
report_methodology -file {{name}}_methodology.rpt
report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
report_power -file {{name}}_power.rpt
{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}