lib.io: Implement *Port from RFC 55.
This commit is contained in:
Wanda
Catherine
parent
744576011f
commit
598cf8db28
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@ -14,17 +14,6 @@ class ResourceError(Exception):
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pass
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class SingleEndedPort:
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def __init__(self, io):
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self.io = io
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class DifferentialPort:
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def __init__(self, p, n):
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self.p = p
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self.n = n
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class PortGroup:
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pass
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@ -138,26 +127,23 @@ class ResourceManager:
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elif isinstance(resource.ios[0], (Pins, DiffPairs)):
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phys = resource.ios[0]
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# The flow is `In` below regardless of requested pin direction. The flow should
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# never be used as it's not used internally and anyone using `dir="-"` should
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# ignore it as well.
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if phys.dir == "oe":
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direction = "o"
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else:
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direction = phys.dir
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if isinstance(phys, Pins):
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phys_names = phys.names
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io = IOPort(len(phys), name="__".join(path) + "__io")
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port = SingleEndedPort(io)
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port = SingleEndedPort(io, invert=phys.invert, direction=direction)
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if isinstance(phys, DiffPairs):
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phys_names = []
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p = IOPort(len(phys), name="__".join(path) + "__p")
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n = IOPort(len(phys), name="__".join(path) + "__n")
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if not self.should_skip_port_component(None, attrs, "p"):
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p = IOPort(len(phys), name="__".join(path) + "__p")
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phys_names += phys.p.names
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else:
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p = None
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if not self.should_skip_port_component(None, attrs, "n"):
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n = IOPort(len(phys), name="__".join(path) + "__n")
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phys_names += phys.n.names
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else:
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n = None
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port = DifferentialPort(p, n)
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port = DifferentialPort(p, n, invert=phys.invert, direction=direction)
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if dir == "-":
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pin = None
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else:
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@ -1,10 +1,256 @@
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from .. import *
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import enum
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from collections.abc import Iterable
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from ..hdl import *
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from ..lib import wiring
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from ..lib.wiring import In, Out
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from .. import tracer
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__all__ = ["Pin"]
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__all__ = ["Direction", "SingleEndedPort", "DifferentialPort", "Pin"]
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class Direction(enum.Enum):
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"""Represents a direction of an I/O port, or of an I/O buffer."""
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#: Input direction (from world to Amaranth design)
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Input = "i"
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#: Output direction (from Amaranth design to world)
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Output = "o"
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#: Bidirectional (can be switched between input and output)
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Bidir = "io"
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def __or__(self, other):
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if not isinstance(other, Direction):
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return NotImplemented
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if self == other:
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return self
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else:
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return Direction.Bidir
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def __and__(self, other):
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if not isinstance(other, Direction):
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return NotImplemented
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if self == other:
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return self
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elif self is Direction.Bidir:
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return other
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elif other is Direction.Bidir:
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return self
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else:
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raise ValueError("Cannot combine input port with output port")
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class SingleEndedPort:
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"""Represents a single-ended I/O port with optional inversion.
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Parameters
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----------
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io : IOValue
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The raw I/O value being wrapped.
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invert : bool or iterable of bool
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If true, the electrical state of the physical pin will be opposite from the Amaranth value
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(the ``*Buffer`` classes will insert inverters on ``o`` and ``i`` pins, as appropriate).
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This can be used for various purposes:
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- Normalizing active-low pins (such as ``CS_B``) to be active-high in Amaranth code
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- Compensating for boards where an inverting level-shifter (or similar circuitry) was used
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on the pin
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If the value is a simple :class:`bool`, it is used for all bits of this port. If the value
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is an iterable of :class:`bool`, the iterable must have the same length as ``io``, and
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the inversion is specified per-bit.
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direction : Direction or str
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Represents the allowed directions of this port. If equal to :attr:`Direction.Input` or
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:attr:`Direction.Output`, this port can only be used with buffers of matching direction.
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If equal to :attr:`Direction.Bidir`, this port can be used with buffers of any direction.
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If a string is passed, it is cast to :class:`Direction`.
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"""
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def __init__(self, io, *, invert=False, direction=Direction.Bidir):
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self._io = IOValue.cast(io)
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if isinstance(invert, bool):
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self._invert = (invert,) * len(self._io)
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elif isinstance(invert, Iterable):
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self._invert = tuple(invert)
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if len(self._invert) != len(self._io):
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raise ValueError(f"Length of 'invert' ({len(self._invert)}) doesn't match "
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f"length of 'io' ({len(self._io)})")
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if not all(isinstance(item, bool) for item in self._invert):
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raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
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else:
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raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
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self._direction = Direction(direction)
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@property
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def io(self):
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"""The ``io`` argument passed to the constructor."""
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return self._io
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@property
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def invert(self):
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"""The ``invert`` argument passed to the constructor, normalized to a :class:`tuple`
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of :class:`bool`."""
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return self._invert
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@property
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def direction(self):
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"""The ``direction`` argument passed to the constructor, normalized to :class:`Direction`."""
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return self._direction
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def __len__(self):
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"""Returns the width of this port in bits. Equal to :py:`len(self.io)`."""
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return len(self._io)
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def __invert__(self):
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"""Returns a new :class:`SingleEndedPort` with the opposite value of ``invert``."""
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return SingleEndedPort(self._io, invert=tuple(not inv for inv in self._invert),
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direction=self._direction)
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def __getitem__(self, index):
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"""Slices the port, returning another :class:`SingleEndedPort` with a subset
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of its bits.
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The index can be a :class:`slice` or :class:`int`. If the index is
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an :class:`int`, the result is a single-bit :class:`SingleEndedPort`."""
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return SingleEndedPort(self._io[index], invert=self._invert[index],
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direction=self._direction)
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def __add__(self, other):
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"""Concatenates two :class:`SingleEndedPort` objects together, returning a new
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:class:`SingleEndedPort` object.
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When the concatenated ports have different directions, the conflict is resolved as follows:
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- If a bidirectional port is concatenated with an input port, the result is an input port.
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- If a bidirectional port is concatenated with an output port, the result is an output port.
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- If an input port is concatenated with an output port, :exc:`ValueError` is raised.
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"""
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if not isinstance(other, SingleEndedPort):
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return NotImplemented
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return SingleEndedPort(Cat(self._io, other._io), invert=self._invert + other._invert,
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direction=self._direction | other._direction)
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def __repr__(self):
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if all(self._invert):
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invert = True
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elif not any(self._invert):
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invert = False
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else:
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invert = self._invert
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return f"SingleEndedPort({self._io!r}, invert={invert!r}, direction={self._direction})"
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class DifferentialPort:
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"""Represents a differential I/O port with optional inversion.
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Parameters
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----------
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p : IOValue
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The raw I/O value used as positive (true) half of the port.
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n : IOValue
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The raw I/O value used as negative (complemented) half of the port. Must have the same
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length as ``p``.
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invert : bool or iterable of bool
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If true, the electrical state of the physical pin will be opposite from the Amaranth value
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(the ``*Buffer`` classes will insert inverters on ``o`` and ``i`` pins, as appropriate).
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This can be used for various purposes:
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- Normalizing active-low pins (such as ``CS_B``) to be active-high in Amaranth code
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- Compensating for boards where the P and N pins are swapped (e.g. for easier routing)
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If the value is a simple :class:`bool`, it is used for all bits of this port. If the value
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is an iterable of :class:`bool`, the iterable must have the same length as ``io``, and
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the inversion is specified per-bit.
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direction : Direction or str
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Represents the allowed directions of this port. If equal to :attr:`Direction.Input` or
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:attr:`Direction.Output`, this port can only be used with buffers of matching direction.
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If equal to :attr:`Direction.Bidir`, this port can be used with buffers of any direction.
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If a string is passed, it is cast to :class:`Direction`.
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"""
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def __init__(self, p, n, *, invert=False, direction=Direction.Bidir):
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self._p = IOValue.cast(p)
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self._n = IOValue.cast(n)
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if len(self._p) != len(self._n):
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raise ValueError(f"Length of 'p' ({len(self._p)}) doesn't match length of 'n' "
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f"({len(self._n)})")
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if isinstance(invert, bool):
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self._invert = (invert,) * len(self._p)
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elif isinstance(invert, Iterable):
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self._invert = tuple(invert)
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if len(self._invert) != len(self._p):
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raise ValueError(f"Length of 'invert' ({len(self._invert)}) doesn't match "
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f"length of 'p' ({len(self._p)})")
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if not all(isinstance(item, bool) for item in self._invert):
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raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
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else:
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raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
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self._direction = Direction(direction)
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@property
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def p(self):
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"""The ``p`` argument passed to the constructor."""
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return self._p
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@property
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def n(self):
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"""The ``n`` argument passed to the constructor."""
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return self._n
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@property
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def invert(self):
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"""The ``invert`` argument passed to the constructor, normalized to a :class:`tuple`
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of :class:`bool`."""
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return self._invert
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@property
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def direction(self):
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"""The ``direction`` argument passed to the constructor, normalized to :class:`Direction`."""
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return self._direction
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def __len__(self):
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"""Returns the width of this port in bits. Equal to :py:`len(self.p)` (and :py:`len(self.n)`)."""
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return len(self._p)
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def __invert__(self):
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"""Returns a new :class:`DifferentialPort` with the opposite value of ``invert``."""
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return DifferentialPort(self._p, self._n, invert=tuple(not inv for inv in self._invert),
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direction=self._direction)
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def __getitem__(self, index):
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"""Slices the port, returning another :class:`DifferentialPort` with a subset
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of its bits.
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The index can be a :class:`slice` or :class:`int`. If the index is
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an :class:`int`, the result is a single-bit :class:`DifferentialPort`."""
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return DifferentialPort(self._p[index], self._n[index], invert=self._invert[index],
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direction=self._direction)
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def __add__(self, other):
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"""Concatenates two :class:`DifferentialPort` objects together, returning a new
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:class:`DifferentialPort` object.
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When the concatenated ports have different directions, the conflict is resolved as follows:
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- If a bidirectional port is concatenated with an input port, the result is an input port.
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- If a bidirectional port is concatenated with an output port, the result is an output port.
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- If an input port is concatenated with an output port, :exc:`ValueError` is raised.
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"""
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if not isinstance(other, DifferentialPort):
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return NotImplemented
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return DifferentialPort(Cat(self._p, other._p), Cat(self._n, other._n),
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invert=self._invert + other._invert,
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direction=self._direction | other._direction)
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def __repr__(self):
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if not any(self._invert):
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invert = False
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elif all(self._invert):
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invert = True
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else:
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invert = self._invert
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return f"DifferentialPort({self._p!r}, {self._n!r}, invert={invert!r}, direction={self._direction})"
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class Pin(wiring.PureInterface):
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@ -50,6 +50,7 @@ Implemented RFCs
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.. _RFC 46: https://amaranth-lang.org/rfcs/0046-shape-range-1.html
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.. _RFC 50: https://amaranth-lang.org/rfcs/0050-print.html
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.. _RFC 53: https://amaranth-lang.org/rfcs/0053-ioport.html
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.. _RFC 55: https://amaranth-lang.org/rfcs/0055-lib-io.html
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* `RFC 17`_: Remove ``log2_int``
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* `RFC 27`_: Testbench processes for the simulator
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@ -93,6 +94,7 @@ Standard library changes
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.. currentmodule:: amaranth.lib
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* Added: :mod:`amaranth.lib.memory`. (`RFC 45`_)
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* Added: :class:`amaranth.lib.io.SingleEndedPort`, :class:`amaranth.lib.io.DifferentialPort`. (`RFC 55`_)
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* Removed: (deprecated in 0.4) :mod:`amaranth.lib.scheduler`. (`RFC 19`_)
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* Removed: (deprecated in 0.4) :class:`amaranth.lib.fifo.FIFOInterface` with ``fwft=False``. (`RFC 20`_)
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* Removed: (deprecated in 0.4) :class:`amaranth.lib.fifo.SyncFIFO` with ``fwft=False``. (`RFC 20`_)
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@ -1,5 +1,3 @@
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import warnings
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from amaranth.hdl import *
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from amaranth.sim import *
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from amaranth.lib.io import *
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@ -8,6 +6,169 @@ from amaranth.lib.wiring import *
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from .utils import *
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class DirectionTestCase(FHDLTestCase):
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def test_or(self):
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self.assertIs(Direction.Input | Direction.Input, Direction.Input)
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self.assertIs(Direction.Input | Direction.Output, Direction.Bidir)
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self.assertIs(Direction.Input | Direction.Bidir, Direction.Bidir)
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self.assertIs(Direction.Output | Direction.Input, Direction.Bidir)
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self.assertIs(Direction.Output | Direction.Output, Direction.Output)
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self.assertIs(Direction.Output | Direction.Bidir, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Input, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Output, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Bidir, Direction.Bidir)
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with self.assertRaises(TypeError):
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Direction.Bidir | 3
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def test_and(self):
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self.assertIs(Direction.Input & Direction.Input, Direction.Input)
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self.assertIs(Direction.Input & Direction.Bidir, Direction.Input)
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self.assertIs(Direction.Output & Direction.Output, Direction.Output)
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self.assertIs(Direction.Output & Direction.Bidir, Direction.Output)
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self.assertIs(Direction.Bidir & Direction.Input, Direction.Input)
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self.assertIs(Direction.Bidir & Direction.Output, Direction.Output)
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self.assertIs(Direction.Bidir & Direction.Bidir, Direction.Bidir)
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with self.assertRaisesRegex(ValueError,
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r"Cannot combine input port with output port"):
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Direction.Output & Direction.Input
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with self.assertRaisesRegex(ValueError,
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r"Cannot combine input port with output port"):
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Direction.Input & Direction.Output
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with self.assertRaises(TypeError):
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Direction.Bidir & 3
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class SingleEndedPortTestCase(FHDLTestCase):
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def test_construct(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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self.assertIs(port.io, io)
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self.assertEqual(port.invert, (False, False, False, False))
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self.assertEqual(port.direction, Direction.Bidir)
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self.assertEqual(len(port), 4)
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=False, direction=Direction.Bidir)")
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port = SingleEndedPort(io, invert=True, direction='i')
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self.assertEqual(port.invert, (True, True, True, True))
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=True, direction=Direction.Input)")
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port = SingleEndedPort(io, invert=[True, False, True, False], direction=Direction.Output)
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self.assertIsInstance(port.invert, tuple)
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self.assertEqual(port.invert, (True, False, True, False))
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=(True, False, True, False), direction=Direction.Output)")
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def test_construct_wrong(self):
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io = IOPort(4)
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sig = Signal(4)
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with self.assertRaisesRegex(TypeError,
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r"^Object \(sig sig\) cannot be converted to an IO value$"):
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SingleEndedPort(sig)
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not 3$"):
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SingleEndedPort(io, invert=3)
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not \[1, 2, 3, 4\]$"):
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SingleEndedPort(io, invert=[1, 2, 3, 4])
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with self.assertRaisesRegex(ValueError,
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r"^Length of 'invert' \(5\) doesn't match length of 'io' \(4\)$"):
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SingleEndedPort(io, invert=[False, False, False, False, False])
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with self.assertRaisesRegex(ValueError,
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r"^'bidir' is not a valid Direction$"):
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SingleEndedPort(io, direction="bidir")
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def test_slice(self):
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io = IOPort(8)
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port = SingleEndedPort(io, invert=(True, False, False, True, True, False, False, True), direction="o")
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self.assertRepr(port[2:5], "SingleEndedPort((io-slice (io-port io) 2:5), invert=(False, True, True), direction=Direction.Output)")
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self.assertRepr(port[7], "SingleEndedPort((io-slice (io-port io) 7:8), invert=True, direction=Direction.Output)")
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def test_cat(self):
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ioa = IOPort(3)
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||||
iob = IOPort(2)
|
||||
porta = SingleEndedPort(ioa, direction=Direction.Input)
|
||||
portb = SingleEndedPort(iob, invert=True, direction=Direction.Input)
|
||||
cport = porta + portb
|
||||
self.assertRepr(cport, "SingleEndedPort((io-cat (io-port ioa) (io-port iob)), invert=(False, False, False, True, True), direction=Direction.Input)")
|
||||
with self.assertRaises(TypeError):
|
||||
porta + iob
|
||||
|
||||
def test_invert(self):
|
||||
io = IOPort(4)
|
||||
port = SingleEndedPort(io, invert=[True, False, True, False], direction=Direction.Output)
|
||||
iport = ~port
|
||||
self.assertRepr(iport, "SingleEndedPort((io-port io), invert=(False, True, False, True), direction=Direction.Output)")
|
||||
|
||||
|
||||
class DifferentialPortTestCase(FHDLTestCase):
|
||||
def test_construct(self):
|
||||
iop = IOPort(4)
|
||||
ion = IOPort(4)
|
||||
port = DifferentialPort(iop, ion)
|
||||
self.assertIs(port.p, iop)
|
||||
self.assertIs(port.n, ion)
|
||||
self.assertEqual(port.invert, (False, False, False, False))
|
||||
self.assertEqual(port.direction, Direction.Bidir)
|
||||
self.assertEqual(len(port), 4)
|
||||
self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=False, direction=Direction.Bidir)")
|
||||
port = DifferentialPort(iop, ion, invert=True, direction='i')
|
||||
self.assertEqual(port.invert, (True, True, True, True))
|
||||
self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=True, direction=Direction.Input)")
|
||||
port = DifferentialPort(iop, ion, invert=[True, False, True, False], direction=Direction.Output)
|
||||
self.assertIsInstance(port.invert, tuple)
|
||||
self.assertEqual(port.invert, (True, False, True, False))
|
||||
self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=(True, False, True, False), direction=Direction.Output)")
|
||||
|
||||
def test_construct_wrong(self):
|
||||
iop = IOPort(4)
|
||||
ion = IOPort(4)
|
||||
sig = Signal(4)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Object \(sig sig\) cannot be converted to an IO value$"):
|
||||
DifferentialPort(iop, sig)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Object \(sig sig\) cannot be converted to an IO value$"):
|
||||
DifferentialPort(sig, ion)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Length of 'p' \(4\) doesn't match length of 'n' \(3\)$"):
|
||||
DifferentialPort(iop, ion[:3])
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^'invert' must be a bool or iterable of bool, not 3$"):
|
||||
DifferentialPort(iop, ion, invert=3)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^'invert' must be a bool or iterable of bool, not \[1, 2, 3, 4\]$"):
|
||||
DifferentialPort(iop, ion, invert=[1, 2, 3, 4])
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Length of 'invert' \(5\) doesn't match length of 'p' \(4\)$"):
|
||||
DifferentialPort(iop, ion, invert=[False, False, False, False, False])
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^'bidir' is not a valid Direction$"):
|
||||
DifferentialPort(iop, ion, direction="bidir")
|
||||
|
||||
def test_slice(self):
|
||||
iop = IOPort(8)
|
||||
ion = IOPort(8)
|
||||
port = DifferentialPort(iop, ion, invert=(True, False, False, True, True, False, False, True), direction="o")
|
||||
self.assertRepr(port[2:5], "DifferentialPort((io-slice (io-port iop) 2:5), (io-slice (io-port ion) 2:5), invert=(False, True, True), direction=Direction.Output)")
|
||||
self.assertRepr(port[7], "DifferentialPort((io-slice (io-port iop) 7:8), (io-slice (io-port ion) 7:8), invert=True, direction=Direction.Output)")
|
||||
|
||||
def test_cat(self):
|
||||
ioap = IOPort(3)
|
||||
ioan = IOPort(3)
|
||||
iobp = IOPort(2)
|
||||
iobn = IOPort(2)
|
||||
porta = DifferentialPort(ioap, ioan, direction=Direction.Input)
|
||||
portb = DifferentialPort(iobp, iobn, invert=True, direction=Direction.Input)
|
||||
cport = porta + portb
|
||||
self.assertRepr(cport, "DifferentialPort((io-cat (io-port ioap) (io-port iobp)), (io-cat (io-port ioan) (io-port iobn)), invert=(False, False, False, True, True), direction=Direction.Input)")
|
||||
with self.assertRaises(TypeError):
|
||||
porta + SingleEndedPort(ioap)
|
||||
|
||||
def test_invert(self):
|
||||
iop = IOPort(4)
|
||||
ion = IOPort(4)
|
||||
port = DifferentialPort(iop, ion, invert=[True, False, True, False], direction=Direction.Output)
|
||||
iport = ~port
|
||||
self.assertRepr(iport, "DifferentialPort((io-port iop), (io-port ion), invert=(False, True, False, True), direction=Direction.Output)")
|
||||
|
||||
|
||||
class PinSignatureTestCase(FHDLTestCase):
|
||||
def assertSignatureEqual(self, signature, expected):
|
||||
self.assertEqual(signature.members, Signature(expected).members)
|
||||
|
|
|
|||
Loading…
Reference in a new issue