lib.io: Implement *Port from RFC 55.
This commit is contained in:
Wanda
Catherine
parent
744576011f
commit
598cf8db28
4 changed files with 421 additions and 26 deletions
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@ -1,5 +1,3 @@
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import warnings
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from amaranth.hdl import *
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from amaranth.sim import *
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from amaranth.lib.io import *
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@ -8,6 +6,169 @@ from amaranth.lib.wiring import *
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from .utils import *
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class DirectionTestCase(FHDLTestCase):
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def test_or(self):
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self.assertIs(Direction.Input | Direction.Input, Direction.Input)
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self.assertIs(Direction.Input | Direction.Output, Direction.Bidir)
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self.assertIs(Direction.Input | Direction.Bidir, Direction.Bidir)
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self.assertIs(Direction.Output | Direction.Input, Direction.Bidir)
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self.assertIs(Direction.Output | Direction.Output, Direction.Output)
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self.assertIs(Direction.Output | Direction.Bidir, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Input, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Output, Direction.Bidir)
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self.assertIs(Direction.Bidir | Direction.Bidir, Direction.Bidir)
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with self.assertRaises(TypeError):
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Direction.Bidir | 3
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def test_and(self):
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self.assertIs(Direction.Input & Direction.Input, Direction.Input)
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self.assertIs(Direction.Input & Direction.Bidir, Direction.Input)
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self.assertIs(Direction.Output & Direction.Output, Direction.Output)
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self.assertIs(Direction.Output & Direction.Bidir, Direction.Output)
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self.assertIs(Direction.Bidir & Direction.Input, Direction.Input)
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self.assertIs(Direction.Bidir & Direction.Output, Direction.Output)
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self.assertIs(Direction.Bidir & Direction.Bidir, Direction.Bidir)
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with self.assertRaisesRegex(ValueError,
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r"Cannot combine input port with output port"):
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Direction.Output & Direction.Input
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with self.assertRaisesRegex(ValueError,
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r"Cannot combine input port with output port"):
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Direction.Input & Direction.Output
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with self.assertRaises(TypeError):
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Direction.Bidir & 3
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class SingleEndedPortTestCase(FHDLTestCase):
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def test_construct(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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self.assertIs(port.io, io)
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self.assertEqual(port.invert, (False, False, False, False))
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self.assertEqual(port.direction, Direction.Bidir)
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self.assertEqual(len(port), 4)
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=False, direction=Direction.Bidir)")
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port = SingleEndedPort(io, invert=True, direction='i')
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self.assertEqual(port.invert, (True, True, True, True))
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=True, direction=Direction.Input)")
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port = SingleEndedPort(io, invert=[True, False, True, False], direction=Direction.Output)
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self.assertIsInstance(port.invert, tuple)
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self.assertEqual(port.invert, (True, False, True, False))
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self.assertRepr(port, "SingleEndedPort((io-port io), invert=(True, False, True, False), direction=Direction.Output)")
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def test_construct_wrong(self):
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io = IOPort(4)
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sig = Signal(4)
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with self.assertRaisesRegex(TypeError,
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r"^Object \(sig sig\) cannot be converted to an IO value$"):
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SingleEndedPort(sig)
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not 3$"):
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SingleEndedPort(io, invert=3)
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not \[1, 2, 3, 4\]$"):
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SingleEndedPort(io, invert=[1, 2, 3, 4])
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with self.assertRaisesRegex(ValueError,
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r"^Length of 'invert' \(5\) doesn't match length of 'io' \(4\)$"):
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SingleEndedPort(io, invert=[False, False, False, False, False])
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with self.assertRaisesRegex(ValueError,
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r"^'bidir' is not a valid Direction$"):
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SingleEndedPort(io, direction="bidir")
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def test_slice(self):
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io = IOPort(8)
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port = SingleEndedPort(io, invert=(True, False, False, True, True, False, False, True), direction="o")
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self.assertRepr(port[2:5], "SingleEndedPort((io-slice (io-port io) 2:5), invert=(False, True, True), direction=Direction.Output)")
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self.assertRepr(port[7], "SingleEndedPort((io-slice (io-port io) 7:8), invert=True, direction=Direction.Output)")
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def test_cat(self):
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ioa = IOPort(3)
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iob = IOPort(2)
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porta = SingleEndedPort(ioa, direction=Direction.Input)
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portb = SingleEndedPort(iob, invert=True, direction=Direction.Input)
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cport = porta + portb
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self.assertRepr(cport, "SingleEndedPort((io-cat (io-port ioa) (io-port iob)), invert=(False, False, False, True, True), direction=Direction.Input)")
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with self.assertRaises(TypeError):
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porta + iob
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def test_invert(self):
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io = IOPort(4)
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port = SingleEndedPort(io, invert=[True, False, True, False], direction=Direction.Output)
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iport = ~port
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self.assertRepr(iport, "SingleEndedPort((io-port io), invert=(False, True, False, True), direction=Direction.Output)")
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class DifferentialPortTestCase(FHDLTestCase):
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def test_construct(self):
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iop = IOPort(4)
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ion = IOPort(4)
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port = DifferentialPort(iop, ion)
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self.assertIs(port.p, iop)
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self.assertIs(port.n, ion)
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self.assertEqual(port.invert, (False, False, False, False))
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self.assertEqual(port.direction, Direction.Bidir)
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self.assertEqual(len(port), 4)
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self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=False, direction=Direction.Bidir)")
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port = DifferentialPort(iop, ion, invert=True, direction='i')
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self.assertEqual(port.invert, (True, True, True, True))
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self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=True, direction=Direction.Input)")
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port = DifferentialPort(iop, ion, invert=[True, False, True, False], direction=Direction.Output)
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self.assertIsInstance(port.invert, tuple)
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self.assertEqual(port.invert, (True, False, True, False))
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self.assertRepr(port, "DifferentialPort((io-port iop), (io-port ion), invert=(True, False, True, False), direction=Direction.Output)")
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def test_construct_wrong(self):
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iop = IOPort(4)
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ion = IOPort(4)
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sig = Signal(4)
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with self.assertRaisesRegex(TypeError,
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r"^Object \(sig sig\) cannot be converted to an IO value$"):
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DifferentialPort(iop, sig)
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with self.assertRaisesRegex(TypeError,
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r"^Object \(sig sig\) cannot be converted to an IO value$"):
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DifferentialPort(sig, ion)
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with self.assertRaisesRegex(ValueError,
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r"^Length of 'p' \(4\) doesn't match length of 'n' \(3\)$"):
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DifferentialPort(iop, ion[:3])
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not 3$"):
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DifferentialPort(iop, ion, invert=3)
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with self.assertRaisesRegex(TypeError,
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r"^'invert' must be a bool or iterable of bool, not \[1, 2, 3, 4\]$"):
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DifferentialPort(iop, ion, invert=[1, 2, 3, 4])
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with self.assertRaisesRegex(ValueError,
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r"^Length of 'invert' \(5\) doesn't match length of 'p' \(4\)$"):
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DifferentialPort(iop, ion, invert=[False, False, False, False, False])
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with self.assertRaisesRegex(ValueError,
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r"^'bidir' is not a valid Direction$"):
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DifferentialPort(iop, ion, direction="bidir")
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def test_slice(self):
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iop = IOPort(8)
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ion = IOPort(8)
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port = DifferentialPort(iop, ion, invert=(True, False, False, True, True, False, False, True), direction="o")
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self.assertRepr(port[2:5], "DifferentialPort((io-slice (io-port iop) 2:5), (io-slice (io-port ion) 2:5), invert=(False, True, True), direction=Direction.Output)")
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self.assertRepr(port[7], "DifferentialPort((io-slice (io-port iop) 7:8), (io-slice (io-port ion) 7:8), invert=True, direction=Direction.Output)")
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def test_cat(self):
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ioap = IOPort(3)
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ioan = IOPort(3)
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iobp = IOPort(2)
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iobn = IOPort(2)
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porta = DifferentialPort(ioap, ioan, direction=Direction.Input)
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portb = DifferentialPort(iobp, iobn, invert=True, direction=Direction.Input)
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cport = porta + portb
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self.assertRepr(cport, "DifferentialPort((io-cat (io-port ioap) (io-port iobp)), (io-cat (io-port ioan) (io-port iobn)), invert=(False, False, False, True, True), direction=Direction.Input)")
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with self.assertRaises(TypeError):
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porta + SingleEndedPort(ioap)
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def test_invert(self):
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iop = IOPort(4)
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ion = IOPort(4)
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port = DifferentialPort(iop, ion, invert=[True, False, True, False], direction=Direction.Output)
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iport = ~port
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self.assertRepr(iport, "DifferentialPort((io-port iop), (io-port ion), invert=(False, True, False, True), direction=Direction.Output)")
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class PinSignatureTestCase(FHDLTestCase):
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def assertSignatureEqual(self, signature, expected):
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self.assertEqual(signature.members, Signature(expected).members)
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