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test: generate examples to verilog as part of unit tests.

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This is to make sure 806a62c2 doesn't happen again.
This commit is contained in:
whitequark 2019-07-08 10:12:15 +00:00
parent c14d074fcc
commit 5c63177fc2
2 changed files with 32 additions and 4 deletions
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8
examples/basic/arst.py
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@ -15,7 +15,7 @@ class ClockDivisor(Elaboratable):
if __name__ == "__main__":
ctr = ClockDivisor(factor=16)
m = ctr.elaborate(platform=None)
m.domains += ClockDomain("sync", async_reset=True)
main(m, ports=[ctr.o])
m = Module()
m.domains.sync = sync = ClockDomain("sync", async_reset=True)
m.submodules.ctr = ctr = ClockDivisor(factor=16)
main(m, ports=[ctr.o, sync.clk])