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test: generate examples to verilog as part of unit tests.

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This is to make sure 806a62c2 doesn't happen again.
This commit is contained in:
whitequark 2019-07-08 10:12:15 +00:00
parent c14d074fcc
commit 5c63177fc2
2 changed files with 32 additions and 4 deletions
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8
examples/basic/arst.py
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@ -15,7 +15,7 @@ class ClockDivisor(Elaboratable):
if __name__ == "__main__": if __name__ == "__main__":
ctr = ClockDivisor(factor=16) m = Module()
m = ctr.elaborate(platform=None) m.domains.sync = sync = ClockDomain("sync", async_reset=True)
m.domains += ClockDomain("sync", async_reset=True) m.submodules.ctr = ctr = ClockDivisor(factor=16)
main(m, ports=[ctr.o]) main(m, ports=[ctr.o, sync.clk])

28
nmigen/test/test_examples.py Normal file
View file

@ -0,0 +1,28 @@
import sys
import subprocess
from pathlib import Path
from .tools import *
def example_test(name):
path = (Path(__file__).parent / ".." / ".." / "examples" / name).resolve()
def test_function(self):
subprocess.check_call([sys.executable, path, "generate"], stdout=subprocess.DEVNULL)
return test_function
class ExamplesTestCase(FHDLTestCase):
test_alu = example_test("basic/alu.py")
test_alu_hier = example_test("basic/alu_hier.py")
test_arst = example_test("basic/arst.py")
test_cdc = example_test("basic/cdc.py")
test_ctr = example_test("basic/ctr.py")
test_ctr_ce = example_test("basic/ctr_ce.py")
test_fsm = example_test("basic/fsm.py")
test_gpio = example_test("basic/gpio.py")
test_inst = example_test("basic/inst.py")
test_mem = example_test("basic/mem.py")
test_pmux = example_test("basic/pmux.py")
test_por = example_test("basic/por.py")
test_uart = example_test("basic/uart.py")