parent
ee1ad2daf1
commit
5f9b8ec1eb
18
nmigen/vendor/lattice_ecp5.py
vendored
18
nmigen/vendor/lattice_ecp5.py
vendored
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@ -185,22 +185,22 @@ class LatticeECP5Platform(TemplatedPlatform):
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{{emit_design("verilog")}}
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""",
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"{{name}}.tcl": r"""
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prj_project new -name "{{name}}" -impl "impl" -impl_dir "top_impl" \
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prj_project new -name {{name}} -impl impl -impl_dir top_impl \
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-dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
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-lpf "{{name}}.lpf" \
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-lpf {{name}}.lpf \
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-synthesis synplify
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{% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
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prj_src add "{{file}}"
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{% endfor %}
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prj_src add "{{name}}.v"
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prj_impl option top "{{name}}"
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prj_src add "{{name}}.sdc"
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prj_src add {{name}}.v
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prj_impl option top {{name}}
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prj_src add {{name}}.sdc
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{{get_override("script_project")|default("# (script_project placeholder)")}}
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prj_project save
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prj_run Synthesis -impl "impl" -forceAll
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prj_run Translate -impl "impl" -forceAll
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prj_run Map -impl "impl" -forceAll
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prj_run PAR -impl "impl" -forceAll
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prj_run Synthesis -impl impl -forceAll
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prj_run Translate -impl impl -forceAll
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prj_run Map -impl impl -forceAll
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prj_run PAR -impl impl -forceAll
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prj_run Export -impl "impl" -forceAll -task Bitgen
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{{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
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""",
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