This commit is contained in:
whitequark 2019-01-15 23:09:10 +00:00
parent 655d02d5b8
commit 6191760c30

View file

@ -376,7 +376,7 @@ class _RHSValueCompiler(_ValueCompiler):
self.s.rtlil.cell("$anyconst", ports={
"\\Y": res,
}, params={
"Y_WIDTH": res_bits,
"WIDTH": res_bits,
}, src=src(value.src_loc))
return res
@ -386,7 +386,7 @@ class _RHSValueCompiler(_ValueCompiler):
self.s.rtlil.cell("$anyseq", ports={
"\\Y": res,
}, params={
"Y_WIDTH": res_bits,
"WIDTH": res_bits,
}, src=src(value.src_loc))
return res