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compat.genlib.fsm: import/wrap Migen code.

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This commit is contained in:
whitequark 2018-12-13 12:40:14 +00:00
parent 9661e897e6
commit 6251c95d4e
5 changed files with 230 additions and 11 deletions
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3
nmigen/back/verilog.py
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@ -30,7 +30,8 @@ proc_clean
write_verilog
# Make sure there are no undriven wires in generated RTLIL.
proc
select -assert-none w:* i:* %a %d c:* %co* %a %d n:$* %d
write_ilang x.il
select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
""".format(il_text))
if popen.returncode:
raise YosysError(error.strip())