vendor.fpga.lattice_ice40: implement differential output buffers.
This commit is contained in:
whitequark
parent
41adcc3f97
commit
639e64c388
85
nmigen/vendor/fpga/lattice_ice40.py
vendored
85
nmigen/vendor/fpga/lattice_ice40.py
vendored
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@ -134,16 +134,29 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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assert False
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def _get_dff(self, clk, d, q):
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return Instance("$dff",
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p_CLK_POLARITY=0,
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p_WIDTH=len(d),
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i_CLK=clk,
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i_D=d,
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o_Q=q)
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def _get_io_buffer(self, m, pin, port, extras, o_invert=None):
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def _get_dff(clk, d, q):
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m.submodules += Instance("$dff",
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p_CLK_POLARITY=0,
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p_WIDTH=len(d),
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i_CLK=clk,
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i_D=d,
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o_Q=q)
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def _get_io_buffer(self, pin, port, extras):
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m = Module()
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def _get_inverter(a, invert):
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if invert is None:
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return a
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else:
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y = Signal.like(a, name="{}_x{}".format(a.name, 1 if invert else 0))
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for bit in range(len(a)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=0b01 if invert else 0b10,
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return y
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if "GLOBAL" in extras:
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is_global_input = bool(extras["GLOBAL"])
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@ -151,14 +164,21 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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is_global_input = False
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = _get_inverter(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = _get_inverter(pin.o0, o_invert)
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pin_o1 = _get_inverter(pin.o1, o_invert)
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if "i" in pin.dir and pin.xdr == 2:
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i0_ff = Signal.like(pin.i0, name="{}_ff".format(pin.i0.name))
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i1_ff = Signal.like(pin.i1, name="{}_ff".format(pin.i1.name))
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m.submodules += self._get_dff(pin.i_clk, i0_ff, pin.i0)
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m.submodules += self._get_dff(pin.i_clk, i1_ff, pin.i1)
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_get_dff(pin.i_clk, i0_ff, pin.i0)
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_get_dff(pin.i_clk, i1_ff, pin.i1)
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if "o" in pin.dir and pin.xdr == 2:
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o1_ff = Signal.like(pin.o1, name="{}_ff".format(pin.o1.name))
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m.submodules += self._get_dff(pin.o_clk, pin.o1, o1_ff)
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_get_dff(pin.o_clk, pin_o1, o1_ff)
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for bit in range(len(port)):
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io_args = [
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@ -205,11 +225,11 @@ class LatticeICE40Platform(TemplatedPlatform):
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io_args.append(("o", "D_IN_1", i1_ff))
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if "o" in pin.dir:
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if pin.xdr < 2:
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io_args.append(("i", "D_OUT_0", pin.o[bit]))
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io_args.append(("i", "D_OUT_0", pin_o[bit]))
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elif pin.xdr == 2:
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# Re-register negedge output after it leaves fabric. This increases setup time
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# to an entire cycle, and doesn't add latency.
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io_args.append(("i", "D_OUT_0", pin.o0[bit]))
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io_args.append(("i", "D_OUT_0", pin_o0[bit]))
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io_args.append(("i", "D_OUT_1", o1_ff))
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if pin.dir in ("oe", "io"):
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@ -220,27 +240,33 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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m.submodules += Instance("SB_IO", *io_args)
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return m
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def get_input(self, pin, port, extras):
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self._check_feature("single-ended input", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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return self._get_io_buffer(pin, port, extras)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_output(self, pin, port, extras):
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self._check_feature("single-ended output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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return self._get_io_buffer(pin, port, extras)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_tristate(self, pin, port, extras):
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self._check_feature("single-ended tristate", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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return self._get_io_buffer(pin, port, extras)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_input_output(self, pin, port, extras):
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self._check_feature("single-ended input/output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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return self._get_io_buffer(pin, port, extras)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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return m
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def get_diff_input(self, pin, p_port, n_port, extras):
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self._check_feature("differential input", pin, extras,
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@ -250,7 +276,24 @@ class LatticeICE40Platform(TemplatedPlatform):
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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return self._get_io_buffer(pin, p_port, extras)
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m = Module()
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self._get_io_buffer(m, pin, p_port, extras)
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return m
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def get_diff_output(self, pin, p_port, n_port, extras):
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self._check_feature("differential output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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m = Module()
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# Note that the non-inverting output pin is not driven the same way as a regular
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# output pin. The inverter introduces a delay, so for a non-inverting output pin,
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# an identical delay is introduced by instantiating a LUT. This makes the waveform
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# perfectly symmetric in the xdr=0 case.
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self._get_io_buffer(m, pin, p_port, extras, o_invert=False)
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self._get_io_buffer(m, pin, n_port, extras, o_invert=True)
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return m
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# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
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# termination, which is incompatible for input and output differential I/Os.
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class IceStormProgrammerMixin:
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