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back.rtlil: Generate $anyconst and $anyseq cells.

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William D. Jones 2019-01-15 16:06:19 -05:00 committed by whitequark
parent 77728c2dea
commit 655d02d5b8
1 changed files with 26 additions and 0 deletions
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26
nmigen/back/rtlil.py
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@ -370,6 +370,26 @@ class _RHSValueCompiler(_ValueCompiler):
value_twos_compl = value.value & ((1 << value.nbits) - 1) value_twos_compl = value.value & ((1 << value.nbits) - 1)
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits) return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
def on_AnyConst(self, value):
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyconst", ports={
"\\Y": res,
}, params={
"Y_WIDTH": res_bits,
}, src=src(value.src_loc))
return res
def on_AnySeq(self, value):
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyseq", ports={
"\\Y": res,
}, params={
"Y_WIDTH": res_bits,
}, src=src(value.src_loc))
return res
def on_Signal(self, value): def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value) wire_curr, wire_next = self.s.resolve(value)
return wire_curr return wire_curr
@ -503,6 +523,12 @@ class _LHSValueCompiler(_ValueCompiler):
def on_Const(self, value): def on_Const(self, value):
raise TypeError # :nocov: raise TypeError # :nocov:
def on_AnyConst(self, value):
raise TypeError # :nocov:
def on_AnySeq(self, value):
raise TypeError # :nocov:
def on_Operator(self, value): def on_Operator(self, value):
raise TypeError # :nocov: raise TypeError # :nocov: