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back.verilog: forbid Yosys version range with dangling else bug.

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Fixes #1049.
This commit is contained in:
Catherine 2024-01-23 03:33:36 +00:00
parent 0ea2aa6b69
commit 65d77f03fe
2 changed files with 5 additions and 3 deletions
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4
amaranth/back/verilog.py
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@ -9,7 +9,9 @@ __all__ = ["YosysError", "convert", "convert_fragment"]
def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
# this version requirement needs to be synchronized with the one in pyproject.toml!
yosys = find_yosys(lambda ver: ver >= (0, 35))
# Yosys 0.37 has a critical miscompilation in Verilog backend:
# https://github.com/amaranth-lang/amaranth/issues/1049
yosys = find_yosys(lambda ver: ver >= (0, 35) and not (0, 36, 79) <= ver <= (0, 37, 29))
script = []
script.append(f"read_ilang <<rtlil\n{rtlil_text}\nrtlil")