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sim.pysim: refuse to write VCD files with whitespace in signal names.

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Closes #595.
This commit is contained in:
whitequark 2021-12-11 11:12:25 +00:00
parent b452e0e871
commit 66295fa388
2 changed files with 20 additions and 2 deletions
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17
tests/test_sim.py
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@ -806,8 +806,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.run_until(1e-5)
with self.assertRaisesRegex(ValueError,
r"^Cannot start writing waveforms after advancing simulation time$"):
with sim.write_vcd(open(os.path.devnull, "wt")):
pass
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
pass
class SimulatorRegressionTestCase(FHDLTestCase):
@ -827,3 +828,15 @@ class SimulatorRegressionTestCase(FHDLTestCase):
self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1)
sim.add_process(process)
sim.run()
def test_bug_595(self):
dut = Module()
with dut.FSM(name="name with space"):
with dut.State(0):
pass
sim = Simulator(dut)
with self.assertRaisesRegex(NameError,
r"^Signal 'top\.name with space_state' contains a whitespace character$"):
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
sim.run()