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back.rtlil: only emit each AnyConst/AnySeq cell once.

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These are semantically like signals, not like constants.
This commit is contained in:
whitequark 2019-01-18 01:27:17 +00:00
parent 60089db075
commit 66466a8a0e
2 changed files with 13 additions and 4 deletions
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9
nmigen/back/rtlil.py
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@ -227,6 +227,7 @@ class _ValueCompilerState:
self.wires = ast.SignalDict()
self.driven = ast.SignalDict()
self.ports = ast.SignalDict()
self.anys = ast.ValueDict()
self.expansions = ast.ValueDict()
@ -377,6 +378,9 @@ class _RHSValueCompiler(_ValueCompiler):
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
def on_AnyConst(self, value):
if value in self.s.anys:
return self.s.anys[value]
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyconst", ports={
@ -384,9 +388,13 @@ class _RHSValueCompiler(_ValueCompiler):
}, params={
"WIDTH": res_bits,
}, src=src(value.src_loc))
self.s.anys[value] = res
return res
def on_AnySeq(self, value):
if value in self.s.anys:
return self.s.anys[value]
res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyseq", ports={
@ -394,6 +402,7 @@ class _RHSValueCompiler(_ValueCompiler):
}, params={
"WIDTH": res_bits,
}, src=src(value.src_loc))
self.s.anys[value] = res
return res
def on_Signal(self, value):