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back.rtlil: only emit each AnyConst/AnySeq cell once.

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These are semantically like signals, not like constants.
This commit is contained in:
whitequark 2019-01-18 01:27:17 +00:00
parent 60089db075
commit 66466a8a0e
2 changed files with 13 additions and 4 deletions
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9
nmigen/back/rtlil.py
View file

@ -227,6 +227,7 @@ class _ValueCompilerState:
self.wires = ast.SignalDict() self.wires = ast.SignalDict()
self.driven = ast.SignalDict() self.driven = ast.SignalDict()
self.ports = ast.SignalDict() self.ports = ast.SignalDict()
self.anys = ast.ValueDict()
self.expansions = ast.ValueDict() self.expansions = ast.ValueDict()
@ -377,6 +378,9 @@ class _RHSValueCompiler(_ValueCompiler):
return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits) return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
def on_AnyConst(self, value): def on_AnyConst(self, value):
if value in self.s.anys:
return self.s.anys[value]
res_bits, res_sign = value.shape() res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits) res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyconst", ports={ self.s.rtlil.cell("$anyconst", ports={
@ -384,9 +388,13 @@ class _RHSValueCompiler(_ValueCompiler):
}, params={ }, params={
"WIDTH": res_bits, "WIDTH": res_bits,
}, src=src(value.src_loc)) }, src=src(value.src_loc))
self.s.anys[value] = res
return res return res
def on_AnySeq(self, value): def on_AnySeq(self, value):
if value in self.s.anys:
return self.s.anys[value]
res_bits, res_sign = value.shape() res_bits, res_sign = value.shape()
res = self.s.rtlil.wire(width=res_bits) res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$anyseq", ports={ self.s.rtlil.cell("$anyseq", ports={
@ -394,6 +402,7 @@ class _RHSValueCompiler(_ValueCompiler):
}, params={ }, params={
"WIDTH": res_bits, "WIDTH": res_bits,
}, src=src(value.src_loc)) }, src=src(value.src_loc))
self.s.anys[value] = res
return res return res
def on_Signal(self, value): def on_Signal(self, value):

8
nmigen/hdl/ast.py
View file

@ -255,7 +255,7 @@ class Const(Value):
C = Const # shorthand C = Const # shorthand
class AnyValue(Value): class AnyValue(Value, DUID):
def __init__(self, shape): def __init__(self, shape):
super().__init__(src_loc_at=0) super().__init__(src_loc_at=0)
if isinstance(shape, int): if isinstance(shape, int):
@ -1119,7 +1119,7 @@ class ValueKey:
def __hash__(self): def __hash__(self):
if isinstance(self.value, Const): if isinstance(self.value, Const):
return hash(self.value.value) return hash(self.value.value)
elif isinstance(self.value, Signal): elif isinstance(self.value, (Signal, AnyValue)):
return hash(self.value.duid) return hash(self.value.duid)
elif isinstance(self.value, (ClockSignal, ResetSignal)): elif isinstance(self.value, (ClockSignal, ResetSignal)):
return hash(self.value.domain) return hash(self.value.domain)
@ -1149,7 +1149,7 @@ class ValueKey:
if isinstance(self.value, Const): if isinstance(self.value, Const):
return self.value.value == other.value.value return self.value.value == other.value.value
elif isinstance(self.value, Signal): elif isinstance(self.value, (Signal, AnyValue)):
return self.value is other.value return self.value is other.value
elif isinstance(self.value, (ClockSignal, ResetSignal)): elif isinstance(self.value, (ClockSignal, ResetSignal)):
return self.value.domain == other.value.domain return self.value.domain == other.value.domain
@ -1191,7 +1191,7 @@ class ValueKey:
if isinstance(self.value, Const): if isinstance(self.value, Const):
return self.value < other.value return self.value < other.value
elif isinstance(self.value, Signal): elif isinstance(self.value, (Signal, AnyValue)):
return self.value.duid < other.value.duid return self.value.duid < other.value.duid
elif isinstance(self.value, Slice): elif isinstance(self.value, Slice):
return (ValueKey(self.value.value) < ValueKey(other.value.value) and return (ValueKey(self.value.value) < ValueKey(other.value.value) and