hdl.ast: Fix width for unary minus operator on signed argument.

To properly represent a negation of a signed X-bit quantity we may, in
general, need a signed (X+1)-bit signal — for example, negation of
3-bit -4 is 4, which is not representable in signed 3 bits.

nmigen/hdl/ast.py

@@ -556,10 +556,7 @@ class Operator(Value):
             if self.operator in ("+", "~"):
                 return Shape(a_width, a_signed)
             if self.operator == "-":
-                if not a_signed:
-                    return Shape(a_width + 1, True)
-                else:
-                    return Shape(a_width, a_signed)
+                return Shape(a_width + 1, True)
             if self.operator in ("b", "r|", "r&", "r^"):
                 return Shape(1, False)
         elif len(op_shapes) == 2: