tests: move out of the main package.
Compared to tests in the repository root, tests in the package have
many downsides:
* Unless explicitly excluded in find_packages(), tests and their
support code effectively become a part of public API.
This, unfortunately, happened with FHDLTestCase, which was never
intended for downstream use.
* Even if explicitly excluded from the setuptools package, using
an editable install, or setting PYTHONPATH still allows accessing
the tests.
* Having a sub-package that is present in the source tree but not
exported (or, worse, exported only sometimes) is confusing.
* The name `nmigen.test` cannot be used for anything else, such as
testing utilities that *are* intended for downstream use.
This commit is contained in:
whitequark
parent
ef7a3bcfb1
commit
67b957d4f4
32 changed files with 103 additions and 82 deletions
0
tests/compat/__init__.py
Normal file
0
tests/compat/__init__.py
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16
tests/compat/support.py
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16
tests/compat/support.py
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@ -0,0 +1,16 @@
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from nmigen.compat import *
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from nmigen.compat.fhdl import verilog
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from nmigen._utils import _ignore_deprecated
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class SimCase:
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def setUp(self, *args, **kwargs):
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with _ignore_deprecated():
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self.tb = self.TestBench(*args, **kwargs)
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def test_to_verilog(self):
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verilog.convert(self.tb)
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def run_with(self, generator):
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with _ignore_deprecated():
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run_simulation(self.tb, generator)
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116
tests/compat/test_coding.py
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116
tests/compat/test_coding.py
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@ -0,0 +1,116 @@
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# nmigen: UnusedElaboratable=no
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import unittest
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from nmigen.compat import *
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from nmigen.compat.genlib.coding import *
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from .support import SimCase
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class EncCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.submodules.dut = Encoder(8)
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def test_sizes(self):
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self.assertEqual(len(self.tb.dut.i), 8)
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self.assertEqual(len(self.tb.dut.o), 3)
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self.assertEqual(len(self.tb.dut.n), 1)
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def test_run_sequence(self):
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seq = list(range(1<<8))
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def gen():
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for _ in range(256):
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if seq:
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yield self.tb.dut.i.eq(seq.pop(0))
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yield
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if (yield self.tb.dut.n):
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self.assertNotIn((yield self.tb.dut.i), [1<<i for i in range(8)])
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else:
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self.assertEqual((yield self.tb.dut.i), 1<<(yield self.tb.dut.o))
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self.run_with(gen())
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class PrioEncCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.submodules.dut = PriorityEncoder(8)
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def test_sizes(self):
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self.assertEqual(len(self.tb.dut.i), 8)
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self.assertEqual(len(self.tb.dut.o), 3)
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self.assertEqual(len(self.tb.dut.n), 1)
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def test_run_sequence(self):
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seq = list(range(1<<8))
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def gen():
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for _ in range(256):
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if seq:
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yield self.tb.dut.i.eq(seq.pop(0))
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yield
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i = yield self.tb.dut.i
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if (yield self.tb.dut.n):
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self.assertEqual(i, 0)
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else:
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o = yield self.tb.dut.o
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if o > 0:
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self.assertEqual(i & 1<<(o - 1), 0)
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self.assertGreaterEqual(i, 1<<o)
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self.run_with(gen())
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class DecCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.submodules.dut = Decoder(8)
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def test_sizes(self):
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self.assertEqual(len(self.tb.dut.i), 3)
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self.assertEqual(len(self.tb.dut.o), 8)
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self.assertEqual(len(self.tb.dut.n), 1)
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def test_run_sequence(self):
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seq = list(range(8*2))
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def gen():
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for _ in range(256):
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if seq:
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i = seq.pop()
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yield self.tb.dut.i.eq(i//2)
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yield self.tb.dut.n.eq(i%2)
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yield
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i = yield self.tb.dut.i
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o = yield self.tb.dut.o
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if (yield self.tb.dut.n):
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self.assertEqual(o, 0)
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else:
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self.assertEqual(o, 1<<i)
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self.run_with(gen())
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class SmallPrioEncCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.submodules.dut = PriorityEncoder(1)
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def test_sizes(self):
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self.assertEqual(len(self.tb.dut.i), 1)
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self.assertEqual(len(self.tb.dut.o), 1)
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self.assertEqual(len(self.tb.dut.n), 1)
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def test_run_sequence(self):
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seq = list(range(1))
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def gen():
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for _ in range(5):
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if seq:
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yield self.tb.dut.i.eq(seq.pop(0))
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yield
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i = yield self.tb.dut.i
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if (yield self.tb.dut.n):
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self.assertEqual(i, 0)
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else:
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o = yield self.tb.dut.o
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if o > 0:
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self.assertEqual(i & 1<<(o - 1), 0)
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self.assertGreaterEqual(i, 1<<o)
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self.run_with(gen())
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30
tests/compat/test_constant.py
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30
tests/compat/test_constant.py
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@ -0,0 +1,30 @@
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import unittest
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from nmigen.compat import *
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from .support import SimCase
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class ConstantCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.sigs = [
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(Signal(3), Constant(0), 0),
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(Signal(3), Constant(5), 5),
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(Signal(3), Constant(1, 2), 1),
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(Signal(3), Constant(-1, 7), 7),
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(Signal(3), Constant(0b10101)[:3], 0b101),
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(Signal(3), Constant(0b10101)[1:4], 0b10),
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(Signal(4), Constant(0b1100)[::-1], 0b0011),
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]
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self.comb += [a.eq(b) for a, b, c in self.sigs]
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def test_comparisons(self):
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def gen():
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for s, l, v in self.tb.sigs:
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s = yield s
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self.assertEqual(
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s, int(v),
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"got {}, want {} from literal {}".format(
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s, v, l))
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self.run_with(gen())
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38
tests/compat/test_fifo.py
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38
tests/compat/test_fifo.py
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import unittest
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from itertools import count
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from nmigen.compat import *
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from nmigen.compat.genlib.fifo import SyncFIFO
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from .support import SimCase
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class SyncFIFOCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.submodules.dut = SyncFIFO(64, 2)
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self.sync += [
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If(self.dut.we & self.dut.writable,
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self.dut.din[:32].eq(self.dut.din[:32] + 1),
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self.dut.din[32:].eq(self.dut.din[32:] + 2)
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)
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]
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def test_run_sequence(self):
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seq = list(range(20))
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def gen():
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for cycle in count():
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# fire re and we at "random"
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yield self.tb.dut.we.eq(cycle % 2 == 0)
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yield self.tb.dut.re.eq(cycle % 3 == 0)
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# the output if valid must be correct
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if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
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try:
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i = seq.pop(0)
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except IndexError:
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break
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self.assertEqual((yield self.tb.dut.dout[:32]), i)
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self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
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yield
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self.run_with(gen())
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87
tests/compat/test_fsm.py
Normal file
87
tests/compat/test_fsm.py
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import unittest
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from itertools import count
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from nmigen.compat import *
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from nmigen.compat.genlib.fsm import FSM
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from .support import SimCase
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class FSMCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.ctrl = Signal()
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self.data = Signal()
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self.status = Signal(8)
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self.submodules.dut = FSM()
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self.dut.act("IDLE",
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If(self.ctrl,
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NextState("START")
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)
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)
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self.dut.act("START",
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If(self.data,
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NextState("SET-STATUS-LOW")
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).Else(
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NextState("SET-STATUS")
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)
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)
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self.dut.act("SET-STATUS",
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NextValue(self.status, 0xaa),
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NextState("IDLE")
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)
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self.dut.act("SET-STATUS-LOW",
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NextValue(self.status[:4], 0xb),
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NextState("IDLE")
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)
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def assertState(self, fsm, state):
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self.assertEqual(fsm.decoding[(yield fsm.state)], state)
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def test_next_state(self):
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def gen():
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yield from self.assertState(self.tb.dut, "IDLE")
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yield
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yield from self.assertState(self.tb.dut, "IDLE")
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yield self.tb.ctrl.eq(1)
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yield
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yield from self.assertState(self.tb.dut, "IDLE")
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yield self.tb.ctrl.eq(0)
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yield
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yield from self.assertState(self.tb.dut, "START")
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yield
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yield from self.assertState(self.tb.dut, "SET-STATUS")
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yield self.tb.ctrl.eq(1)
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yield
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yield from self.assertState(self.tb.dut, "IDLE")
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yield self.tb.ctrl.eq(0)
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yield self.tb.data.eq(1)
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yield
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yield from self.assertState(self.tb.dut, "START")
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yield self.tb.data.eq(0)
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yield
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yield from self.assertState(self.tb.dut, "SET-STATUS-LOW")
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self.run_with(gen())
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def test_next_value(self):
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def gen():
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self.assertEqual((yield self.tb.status), 0x00)
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yield self.tb.ctrl.eq(1)
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yield
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yield self.tb.ctrl.eq(0)
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yield
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yield
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yield from self.assertState(self.tb.dut, "SET-STATUS")
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yield self.tb.ctrl.eq(1)
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yield
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self.assertEqual((yield self.tb.status), 0xaa)
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yield self.tb.ctrl.eq(0)
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yield self.tb.data.eq(1)
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yield
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yield self.tb.data.eq(0)
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yield
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yield from self.assertState(self.tb.dut, "SET-STATUS-LOW")
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yield
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self.assertEqual((yield self.tb.status), 0xab)
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self.run_with(gen())
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23
tests/compat/test_passive.py
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23
tests/compat/test_passive.py
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import unittest
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from nmigen.compat import *
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class PassiveCase(unittest.TestCase):
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def test_terminates_correctly(self):
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n = 5
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count = 0
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@passive
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def counter():
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nonlocal count
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while True:
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yield
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count += 1
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def terminator():
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for i in range(n):
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yield
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run_simulation(Module(), [counter(), terminator()])
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self.assertEqual(count, n)
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28
tests/compat/test_run_simulation.py
Normal file
28
tests/compat/test_run_simulation.py
Normal file
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@ -0,0 +1,28 @@
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import unittest
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from nmigen import Signal, Module, Elaboratable
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from .support import SimCase
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class RunSimulation(SimCase, unittest.TestCase):
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""" test for https://github.com/nmigen/nmigen/issues/344 """
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class TestBench(Elaboratable):
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def __init__(self):
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self.a = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.a.eq(~self.a)
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return m
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def test_run_simulation(self):
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def gen():
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yield
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for i in range(10):
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yield
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a = (yield self.tb.a)
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self.assertEqual(a, i % 2)
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self.run_with(gen())
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43
tests/compat/test_signed.py
Normal file
43
tests/compat/test_signed.py
Normal file
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import unittest
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from nmigen.compat import *
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from .support import SimCase
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class SignedCase(SimCase, unittest.TestCase):
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class TestBench(Module):
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def __init__(self):
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self.a = Signal((3, True))
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self.b = Signal((4, True))
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comps = [
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lambda p, q: p > q,
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lambda p, q: p >= q,
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lambda p, q: p < q,
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lambda p, q: p <= q,
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lambda p, q: p == q,
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lambda p, q: p != q,
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]
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self.vals = []
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for asign in 1, -1:
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for bsign in 1, -1:
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for f in comps:
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r = Signal()
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r0 = f(asign*self.a, bsign*self.b)
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self.comb += r.eq(r0)
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self.vals.append((asign, bsign, f, r, r0.op))
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def test_comparisons(self):
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def gen():
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for i in range(-4, 4):
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yield self.tb.a.eq(i)
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yield self.tb.b.eq(i)
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yield
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a = yield self.tb.a
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b = yield self.tb.b
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for asign, bsign, f, r, op in self.tb.vals:
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r, r0 = (yield r), f(asign*a, bsign*b)
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self.assertEqual(r, int(r0),
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"got {}, want {}*{} {} {}*{} = {}".format(
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r, asign, a, op, bsign, b, r0))
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self.run_with(gen())
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21
tests/compat/test_size.py
Normal file
21
tests/compat/test_size.py
Normal file
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import unittest
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from nmigen._utils import _ignore_deprecated
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from nmigen.compat import *
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def _same_slices(a, b):
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return a.value is b.value and a.start == b.start and a.stop == b.stop
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class SignalSizeCase(unittest.TestCase):
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def setUp(self):
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self.i = C(0xaa)
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self.j = C(-127)
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with _ignore_deprecated():
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self.s = Signal((13, True))
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def test_len(self):
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self.assertEqual(len(self.s), 13)
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self.assertEqual(len(self.i), 8)
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self.assertEqual(len(self.j), 8)
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Loading…
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