parent
a9da9efe5b
commit
687d3a3df7
2 changed files with 14 additions and 0 deletions
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@ -400,6 +400,8 @@ class DSLTestCase(FHDLTestCase):
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""")
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def test_Case_width_wrong(self):
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class Color(Enum):
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RED = 0b10101010
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m = Module()
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with m.Switch(self.w1):
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with self.assertRaises(SyntaxError,
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@ -411,6 +413,11 @@ class DSLTestCase(FHDLTestCase):
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"comparison will never be true"):
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with m.Case(0b10110):
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pass
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with self.assertWarns(SyntaxWarning,
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msg="Case pattern '10101010' (Color.RED) is wider than switch value "
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"(which has width 4); comparison will never be true"):
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with m.Case(Color.RED):
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pass
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self.assertRepr(m._statements, """
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(
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(switch (sig w1) )
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