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hdl.dsl: add getters to m.submodules.

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This commit is contained in:
N. Engelhardt 2019-07-19 20:39:47 +08:00 • committed by whitequark
parent 81e59832fb
commit 698b005182
2 changed files with 60 additions and 8 deletions
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40
nmigen/test/test_hdl_dsl.py
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@ -517,26 +517,30 @@ class DSLTestCase(FHDLTestCase):
m1 = Module()
m2 = Module()
m1.submodules += m2
self.assertEqual(m1._submodules, [(m2, None)])
self.assertEqual(m1._anon_submodules, [m2])
self.assertEqual(m1._named_submodules, {})
def test_submodule_anon_multi(self):
m1 = Module()
m2 = Module()
m3 = Module()
m1.submodules += m2, m3
self.assertEqual(m1._submodules, [(m2, None), (m3, None)])
self.assertEqual(m1._anon_submodules, [m2, m3])
self.assertEqual(m1._named_submodules, {})
def test_submodule_named(self):
m1 = Module()
m2 = Module()
m1.submodules.foo = m2
self.assertEqual(m1._submodules, [(m2, "foo")])
self.assertEqual(m1._anon_submodules, [])
self.assertEqual(m1._named_submodules, {"foo": m2})
def test_submodule_named_index(self):
m1 = Module()
m2 = Module()
m1.submodules["foo"] = m2
self.assertEqual(m1._submodules, [(m2, "foo")])
self.assertEqual(m1._anon_submodules, [])
self.assertEqual(m1._named_submodules, {"foo": m2})
def test_submodule_wrong(self):
m = Module()
@ -547,6 +551,34 @@ class DSLTestCase(FHDLTestCase):
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
m.submodules += 1
def test_submodule_named_conflict(self):
m1 = Module()
m2 = Module()
m1.submodules.foo = m2
with self.assertRaises(NameError, msg="Submodule named 'foo' already exists"):
m1.submodules.foo = m2
def test_submodule_get(self):
m1 = Module()
m2 = Module()
m1.submodules.foo = m2
m3 = m1.submodules.foo
self.assertEqual(m2, m3)
def test_submodule_get_index(self):
m1 = Module()
m2 = Module()
m1.submodules["foo"] = m2
m3 = m1.submodules["foo"]
self.assertEqual(m2, m3)
def test_submodule_get_unset(self):
m1 = Module()
with self.assertRaises(AttributeError, msg="No submodule named 'foo' exists"):
m2 = m1.submodules.foo
with self.assertRaises(AttributeError, msg="No submodule named 'foo' exists"):
m2 = m1.submodules["foo"]
def test_domain_named_implicit(self):
m = Module()
m.domains += ClockDomain("sync")