parent
c649045f35
commit
6a2e789333
2 changed files with 62 additions and 5 deletions
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@ -1472,8 +1472,8 @@ class SimulatorRegressionTestCase(FHDLTestCase):
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dut.d.sync += Signal().eq(0)
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sim = Simulator(dut)
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with self.assertWarnsRegex(UserWarning,
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r"^Adding a clock process that drives a clock domain object named 'sync', "
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r"which is distinct from an identically named domain in the simulated design$"):
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r"^Adding a clock that drives a clock domain object named 'sync', which is "
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r"distinct from an identically named domain in the simulated design$"):
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sim.add_clock(1e-6, domain=ClockDomain("sync"))
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def test_bug_826(self):
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@ -2009,3 +2009,40 @@ class SimulatorRegressionTestCase(FHDLTestCase):
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async def testbench():
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yield Delay()
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sim.add_testbench(testbench())
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def test_issue_1368(self):
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sim = Simulator(Module())
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async def testbench(ctx):
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sim.add_clock(1e-6)
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sim.add_testbench(testbench)
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with self.assertRaisesRegex(RuntimeError,
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r"^Cannot add a clock to a running simulation$"):
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sim.run()
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sim = Simulator(Module())
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async def testbench(ctx):
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async def testbench2(ctx):
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pass
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sim.add_testbench(testbench2)
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sim.add_testbench(testbench)
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with self.assertRaisesRegex(RuntimeError,
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r"^Cannot add a testbench to a running simulation$"):
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sim.run()
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sim = Simulator(Module())
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async def process(ctx):
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async def process2(ctx):
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pass
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sim.add_process(process2)
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sim.add_process(process)
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with self.assertRaisesRegex(RuntimeError,
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r"^Cannot add a process to a running simulation$"):
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sim.run()
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async def process_empty(ctx):
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pass
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sim = Simulator(Module())
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sim.run()
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sim.reset()
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sim.add_process(process_empty) # should succeed
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sim.run() # suppress 'coroutine was never awaited' warning
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