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back.pysim: fix handling of process termination.

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This commit is contained in:
whitequark 2018-12-13 18:17:58 +00:00
parent fb27c2520b
commit 6a4004ef8d
2 changed files with 13 additions and 3 deletions
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13
examples/ctrl.py
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@ -1,5 +1,5 @@
from nmigen.fhdl import *
from nmigen.back import rtlil, verilog
from nmigen.back import rtlil, verilog, pysim
class ClockDivisor:
@ -17,5 +17,16 @@ class ClockDivisor:
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
sim.add_clock("sync", 1e-6)
def sim_proc():
yield pysim.Delay(15.25e-6)
yield ctr.ce.eq(Const(1))
yield pysim.Delay(15e-6)
yield ctr.ce.eq(Const(0))
sim.add_process(sim_proc())
with sim: sim.run_until(100e-6, run_passive=True)