usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

hdl.rec: implement slicing by component names.

Browse source 
Fixes #121.
This commit is contained in:
whitequark 2019-07-02 17:44:55 +00:00
parent 34f110100a
commit 6b843b5be6
2 changed files with 34 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

19
nmigen/test/test_hdl_rec.py
View file

@ -25,6 +25,18 @@ class LayoutTestCase(FHDLTestCase):
self.assertEqual(sublayout["a"], ((1, False), DIR_NONE))
self.assertEqual(sublayout["b"], ((1, False), DIR_NONE))
def test_slice_tuple(self):
layout = Layout.wrap([
("a", 1),
("b", 2),
("c", 3)
])
expect = Layout.wrap([
("a", 1),
("c", 3)
])
self.assertEqual(layout["a", "c"], expect)
def test_wrong_field(self):
with self.assertRaises(TypeError,
msg="Field (1,) has invalid layout: should be either (name, shape) or "
@ -139,6 +151,13 @@ class RecordTestCase(FHDLTestCase):
r4 = Record.like(r1, name_suffix="foo")
self.assertEqual(r4.name, "r1foo")
def test_slice_tuple(self):
r1 = Record([("a", 1), ("b", 2), ("c", 3)])
r2 = r1["a", "c"]
self.assertEqual(r2.layout, Layout([("a", 1), ("c", 3)]))
self.assertIs(r2.a, r1.a)
self.assertIs(r2.c, r1.c)
class ConnectTestCase(FHDLTestCase):
def setUp_flat(self):