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hdl, back.rtlil: track and emit module/submodule locations.

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Wanda 2024-02-16 16:16:26 +01:00 • committed by Catherine
parent 188eb8d453
commit 6d65dc1366
10 changed files with 82 additions and 67 deletions
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15
tests/test_hdl_dsl.py
View file

@ -830,7 +830,8 @@ class DSLTestCase(FHDLTestCase):
m1 = Module()
m2 = Module()
m1.submodules += m2
self.assertEqual(m1._anon_submodules, [m2])
self.assertEqual(len(m1._anon_submodules), 1)
self.assertEqual(m1._anon_submodules[0][0], m2)
self.assertEqual(m1._named_submodules, {})
def test_submodule_anon_multi(self):
@ -838,7 +839,9 @@ class DSLTestCase(FHDLTestCase):
m2 = Module()
m3 = Module()
m1.submodules += m2, m3
self.assertEqual(m1._anon_submodules, [m2, m3])
self.assertEqual(len(m1._anon_submodules), 2)
self.assertEqual(m1._anon_submodules[0][0], m2)
self.assertEqual(m1._anon_submodules[1][0], m3)
self.assertEqual(m1._named_submodules, {})
def test_submodule_named(self):
@ -846,14 +849,16 @@ class DSLTestCase(FHDLTestCase):
m2 = Module()
m1.submodules.foo = m2
self.assertEqual(m1._anon_submodules, [])
self.assertEqual(m1._named_submodules, {"foo": m2})
self.assertEqual(m1._named_submodules.keys(), {"foo"})
self.assertEqual(m1._named_submodules["foo"][0], m2)
def test_submodule_named_index(self):
m1 = Module()
m2 = Module()
m1.submodules["foo"] = m2
self.assertEqual(m1._anon_submodules, [])
self.assertEqual(m1._named_submodules, {"foo": m2})
self.assertEqual(m1._named_submodules.keys(), {"foo"})
self.assertEqual(m1._named_submodules["foo"][0], m2)
def test_submodule_wrong(self):
m = Module()
@ -943,7 +948,7 @@ class DSLTestCase(FHDLTestCase):
"comb": SignalSet((self.c1,))
})
self.assertEqual(len(f1.subfragments), 1)
(f2, f2_name), = f1.subfragments
(f2, f2_name, _), = f1.subfragments
self.assertEqual(f2_name, "foo")
self.assertRepr(f2.statements["comb"], """
(

10
tests/test_hdl_ir.py
View file

@ -392,7 +392,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
f._propagate_domains_up()
self.assertEqual(f.domains, {"a_sync": cda, "b_sync": cdb})
(fa, _), (fb, _) = f.subfragments
(fa, _, _), (fb, _, _) = f.subfragments
self.assertEqual(fa.domains, {"a_sync": cda})
self.assertEqual(fb.domains, {"b_sync": cdb})
@ -446,7 +446,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
f.add_subfragment(fb, "b")
f._propagate_domains_up()
fb_new, _ = f.subfragments[1]
fb_new, _, _ = f.subfragments[1]
self.assertEqual(fb_new.drivers, OrderedDict({
"comb": SignalSet((ResetSignal("b_sync"),))
}))
@ -540,7 +540,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
self.assertEqual(f1.domains["sync"], f2.domains["sync"])
self.assertEqual(new_domains, [])
self.assertEqual(f1.subfragments, [
(f2, "cd_sync")
(f2, "cd_sync", None)
])
def test_propagate_create_missing_fragment_many_domains(self):
@ -559,7 +559,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
self.assertEqual(f1.domains["sync"], f2.domains["sync"])
self.assertEqual(new_domains, [])
self.assertEqual(f1.subfragments, [
(f2, "cd_sync")
(f2, "cd_sync", None)
])
def test_propagate_create_missing_fragment_wrong(self):
@ -606,7 +606,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
self.setUp_self_sub()
self.f1._resolve_hierarchy_conflicts(mode="silent")
self.assertEqual(self.f1.subfragments, [
self.assertEqual([(f, n) for f, n, _ in self.f1.subfragments], [
(self.f1a, "f1a"),
(self.f1b, "f1b"),
(self.f2a, "f2a"),

2
tests/test_hdl_xfrm.py
View file

@ -378,7 +378,7 @@ class EnableInserterTestCase(FHDLTestCase):
f1.add_subfragment(f2)
f1 = EnableInserter(self.c1)(f1)
(f2, _), = f1.subfragments
(f2, _, _), = f1.subfragments
self.assertRepr(f1.statements["sync"], """
(
(eq (sig s1) (const 1'd1))