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vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.

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Fixes #438 (again).
This commit is contained in:
whitequark 2020-08-26 10:18:02 +00:00
parent abaa9091f4
commit 6d9852506f
2 changed files with 8 additions and 9 deletions
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7
nmigen/vendor/xilinx_7series.py
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@ -317,10 +317,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
ready = Signal()
m.submodules += Instance("STARTUPE2", o_EOS=ready)
m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
# Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
# mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
# breaks Vivado 2017.4.
# Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes
# sim/synth mismatches with Vivado 2019.2, and the suggested workaround
# (SIM_DEVICE parameter) breaks Vivado 2017.4.
m.submodules += Instance("BUFGCTRL",
p_SIM_DEVICE="7SERIES",
i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1),
i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
o_O=ClockSignal("sync")

10
nmigen/vendor/xilinx_ultrascale.py
View file

@ -168,12 +168,10 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
ready = Signal()
m.submodules += Instance("STARTUPE3", o_EOS=ready)
m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
# Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
# mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
# breaks Vivado 2017.4.
m.submodules += Instance("BUFGCTRL",
i_I0=clk_i, i_S0=C(1, 1), i_CE0=ready, i_IGNORE0=C(0, 1),
i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
m.submodules += Instance("BUFGCE",
p_SIM_DEVICE="ULTRASCALE",
i_CE=ready,
i_I=clk_i,
o_O=ClockSignal("sync")
)
if self.default_rst is not None: