Wanda
Catherine
parent
09854fa775
commit
6e06fc013f
12 changed files with 313 additions and 196 deletions
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@ -34,7 +34,7 @@ class DSLTestCase(FHDLTestCase):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], None)
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self.assertRepr(m._statements, """(
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self.assertRepr(m._statements[None], """(
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(eq (sig c1) (const 1'd1))
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)""")
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@ -43,7 +43,7 @@ class DSLTestCase(FHDLTestCase):
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m.d.sync += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "sync")
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self.assertRepr(m._statements, """(
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self.assertRepr(m._statements["sync"], """(
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(eq (sig c1) (const 1'd1))
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)""")
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@ -52,7 +52,7 @@ class DSLTestCase(FHDLTestCase):
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m.d.pix += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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self.assertRepr(m._statements["pix"], """(
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(eq (sig c1) (const 1'd1))
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)""")
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@ -61,7 +61,7 @@ class DSLTestCase(FHDLTestCase):
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m.d["pix"] += self.c1.eq(1)
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m._flush()
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self.assertEqual(m._driving[self.c1], "pix")
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self.assertRepr(m._statements, """(
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self.assertRepr(m._statements["pix"], """(
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(eq (sig c1) (const 1'd1))
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)""")
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@ -118,7 +118,7 @@ class DSLTestCase(FHDLTestCase):
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def test_clock_signal(self):
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m = Module()
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m.d.comb += ClockSignal("pix").eq(ClockSignal())
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(eq (clk pix) (clk sync))
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)
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@ -127,7 +127,7 @@ class DSLTestCase(FHDLTestCase):
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def test_reset_signal(self):
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m = Module()
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m.d.comb += ResetSignal("pix").eq(1)
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(eq (rst pix) (const 1'd1))
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)
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@ -138,7 +138,7 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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@ -151,9 +151,9 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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m.d.comb += self.c2.eq(0)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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@ -162,6 +162,30 @@ class DSLTestCase(FHDLTestCase):
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)
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""")
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def test_If_Elif_multi(self):
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m = Module()
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with m.If(self.s1):
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m.d.comb += self.c1.eq(1)
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with m.Elif(self.s2):
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m.d.sync += self.c2.eq(0)
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m._flush()
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- )
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)
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)
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""")
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self.assertRepr(m._statements["sync"], """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 )
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(case 1- (eq (sig c2) (const 1'd0)))
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)
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)
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""")
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def test_If_Elif_Else(self):
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m = Module()
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with m.If(self.s1):
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@ -171,15 +195,24 @@ class DSLTestCase(FHDLTestCase):
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 (eq (sig c1) (const 1'd1)))
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(case 1- (eq (sig c2) (const 1'd0)))
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(case 1- )
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(default (eq (sig c3) (const 1'd1)))
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)
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)
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""")
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self.assertRepr(m._statements["sync"], """
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(
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(switch (cat (sig s1) (sig s2))
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(case -1 )
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(case 1- (eq (sig c2) (const 1'd0)))
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(default )
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)
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)
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""")
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def test_If_If(self):
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m = Module()
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@ -188,7 +221,7 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1)))
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@ -206,7 +239,7 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.s2):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1))
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(case 1 (eq (sig c1) (const 1'd1))
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@ -227,7 +260,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Else():
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m.d.comb += self.c3.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (sig s1))
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(case 1
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@ -298,7 +331,7 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.w1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (b (sig w1)))
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(case 1 (eq (sig c1) (const 1'd1)))
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@ -356,7 +389,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Case("1 0--"):
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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@ -374,7 +407,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Case():
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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@ -390,7 +423,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Default():
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m.d.comb += self.c2.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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@ -405,7 +438,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Case(1):
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m.d.comb += self.c1.eq(1)
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (const 1'd1)
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(case 1 (eq (sig c1) (const 1'd1)))
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@ -422,7 +455,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Switch(se):
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with m.Case(Color.RED):
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m.d.comb += self.c1.eq(1)
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig se)
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(case 01 (eq (sig c1) (const 1'd1)))
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@ -439,7 +472,7 @@ class DSLTestCase(FHDLTestCase):
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with m.Switch(se):
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with m.Case(Cat(Color.RED, Color.BLUE)):
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m.d.comb += self.c1.eq(1)
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig se)
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(case 10 (eq (sig c1) (const 1'd1)))
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@ -451,26 +484,23 @@ class DSLTestCase(FHDLTestCase):
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class Color(Enum):
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RED = 0b10101010
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m = Module()
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dummy = Signal()
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with m.Switch(self.w1):
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with self.assertRaisesRegex(SyntaxError,
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r"^Case pattern '--' must have the same width as switch value \(which is 4\)$"):
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with m.Case("--"):
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pass
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m.d.comb += dummy.eq(0)
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Case pattern '22' \(5'10110\) is wider than switch value \(which has "
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r"width 4\); comparison will never be true$"):
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with m.Case(0b10110):
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pass
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m.d.comb += dummy.eq(0)
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Case pattern '<Color.RED: 170>' \(8'10101010\) is wider than switch value "
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r"\(which has width 4\); comparison will never be true$"):
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with m.Case(Color.RED):
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pass
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self.assertRepr(m._statements, """
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(
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(switch (sig w1) )
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)
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""")
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m.d.comb += dummy.eq(0)
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self.assertEqual(m._statements, {})
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def test_Case_bits_wrong(self):
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m = Module()
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@ -549,11 +579,20 @@ class DSLTestCase(FHDLTestCase):
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with m.If(c):
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m.next = "FIRST"
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig a) (const 1'd1))
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)
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(case 1 )
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)
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)
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""")
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self.assertRepr(m._statements["sync"], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig fsm_state) (const 1'd1))
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)
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(case 1
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@ -594,11 +633,20 @@ class DSLTestCase(FHDLTestCase):
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with m.State("SECOND"):
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m.next = "FIRST"
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m._flush()
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig a) (const 1'd0))
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)
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(case 1 )
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)
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)
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""")
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self.assertRepr(m._statements["sync"], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig fsm_state) (const 1'd1))
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)
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(case 1
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@ -622,16 +670,10 @@ class DSLTestCase(FHDLTestCase):
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m._flush()
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self.assertEqual(m._generated["fsm"].state.reset, 1)
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self.maxDiff = 10000
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(eq (sig b) (== (sig fsm_state) (const 1'd0)))
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(eq (sig a) (== (sig fsm_state) (const 1'd1)))
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(switch (sig fsm_state)
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(case 1
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)
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(case 0
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)
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)
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)
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""")
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@ -639,9 +681,7 @@ class DSLTestCase(FHDLTestCase):
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m = Module()
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with m.FSM():
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pass
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self.assertRepr(m._statements, """
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()
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""")
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self.assertEqual(m._statements, {})
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def test_FSM_wrong_domain(self):
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m = Module()
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@ -713,7 +753,7 @@ class DSLTestCase(FHDLTestCase):
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with m.If(self.w1):
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m.d.comb += self.c1.eq(1)
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m.d.comb += self.c2.eq(1)
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self.assertRepr(m._statements, """
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self.assertRepr(m._statements[None], """
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(
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(switch (cat (b (sig w1)))
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(case 1 (eq (sig c1) (const 1'd1)))
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@ -830,7 +870,7 @@ class DSLTestCase(FHDLTestCase):
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m1.submodules.foo = m2
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f1 = m1.elaborate(platform=None)
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self.assertRepr(f1.statements, """
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self.assertRepr(f1.statements[None], """
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(
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(eq (sig c1) (sig s1))
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)
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@ -841,9 +881,13 @@ class DSLTestCase(FHDLTestCase):
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self.assertEqual(len(f1.subfragments), 1)
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(f2, f2_name), = f1.subfragments
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self.assertEqual(f2_name, "foo")
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self.assertRepr(f2.statements, """
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self.assertRepr(f2.statements[None], """
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(
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(eq (sig c2) (sig s2))
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)
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""")
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self.assertRepr(f2.statements["sync"], """
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(
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(eq (sig c3) (sig s3))
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)
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""")
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@ -100,6 +100,7 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_self_contained(self):
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f = Fragment()
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f.add_statements(
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None,
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self.c1.eq(self.s1),
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self.s1.eq(self.c1)
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)
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@ -110,6 +111,7 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_infer_input(self):
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f = Fragment()
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f.add_statements(
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None,
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self.c1.eq(self.s1)
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)
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@ -121,6 +123,7 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_request_output(self):
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f = Fragment()
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f.add_statements(
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None,
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self.c1.eq(self.s1)
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)
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@ -133,10 +136,12 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_input_in_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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None,
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self.c1.eq(self.s1)
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)
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f2 = Fragment()
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f2.add_statements(
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None,
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self.s1.eq(0)
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)
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f1.add_subfragment(f2)
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@ -150,6 +155,7 @@ class FragmentPortsTestCase(FHDLTestCase):
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f1 = Fragment()
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f2 = Fragment()
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f2.add_statements(
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None,
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self.c1.eq(self.s1)
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)
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f1.add_subfragment(f2)
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@ -164,10 +170,12 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_output_from_subfragment(self):
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f1 = Fragment()
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f1.add_statements(
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None,
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self.c1.eq(0)
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)
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f2 = Fragment()
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f2.add_statements(
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None,
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self.c2.eq(1)
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)
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f1.add_subfragment(f2)
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@ -183,15 +191,18 @@ class FragmentPortsTestCase(FHDLTestCase):
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def test_output_from_subfragment_2(self):
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f1 = Fragment()
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f1.add_statements(
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None,
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self.c1.eq(self.s1)
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)
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f2 = Fragment()
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f2.add_statements(
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None,
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self.c2.eq(self.s1)
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)
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f1.add_subfragment(f2)
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f3 = Fragment()
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f3.add_statements(
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None,
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self.s1.eq(0)
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)
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f2.add_subfragment(f3)
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@ -205,11 +216,13 @@ class FragmentPortsTestCase(FHDLTestCase):
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f1 = Fragment()
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f2 = Fragment()
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f2.add_statements(
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None,
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self.c1.eq(self.c2)
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)
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f1.add_subfragment(f2)
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f3 = Fragment()
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f3.add_statements(
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None,
|
||||
self.c2.eq(0)
|
||||
)
|
||||
f3.add_driver(self.c2)
|
||||
|
|
@ -222,12 +235,14 @@ class FragmentPortsTestCase(FHDLTestCase):
|
|||
f1 = Fragment()
|
||||
f2 = Fragment()
|
||||
f2.add_statements(
|
||||
None,
|
||||
self.c2.eq(0)
|
||||
)
|
||||
f2.add_driver(self.c2)
|
||||
f1.add_subfragment(f2)
|
||||
f3 = Fragment()
|
||||
f3.add_statements(
|
||||
None,
|
||||
self.c1.eq(self.c2)
|
||||
)
|
||||
f1.add_subfragment(f3)
|
||||
|
|
@ -239,6 +254,7 @@ class FragmentPortsTestCase(FHDLTestCase):
|
|||
sync = ClockDomain()
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
self.c1.eq(self.s1)
|
||||
)
|
||||
f.add_domains(sync)
|
||||
|
|
@ -255,6 +271,7 @@ class FragmentPortsTestCase(FHDLTestCase):
|
|||
sync = ClockDomain(reset_less=True)
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
self.c1.eq(self.s1)
|
||||
)
|
||||
f.add_domains(sync)
|
||||
|
|
@ -490,7 +507,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
|
|||
def test_propagate_missing(self):
|
||||
s1 = Signal()
|
||||
f1 = Fragment()
|
||||
f1.add_driver(s1, "sync")
|
||||
f1.add_statements("sync", s1.eq(1))
|
||||
|
||||
with self.assertRaisesRegex(DomainError,
|
||||
r"^Domain 'sync' is used but not defined$"):
|
||||
|
|
@ -499,7 +516,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
|
|||
def test_propagate_create_missing(self):
|
||||
s1 = Signal()
|
||||
f1 = Fragment()
|
||||
f1.add_driver(s1, "sync")
|
||||
f1.add_statements("sync", s1.eq(1))
|
||||
f2 = Fragment()
|
||||
f1.add_subfragment(f2)
|
||||
|
||||
|
|
@ -512,7 +529,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
|
|||
def test_propagate_create_missing_fragment(self):
|
||||
s1 = Signal()
|
||||
f1 = Fragment()
|
||||
f1.add_driver(s1, "sync")
|
||||
f1.add_statements("sync", s1.eq(1))
|
||||
|
||||
cd = ClockDomain("sync")
|
||||
f2 = Fragment()
|
||||
|
|
@ -529,7 +546,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
|
|||
def test_propagate_create_missing_fragment_many_domains(self):
|
||||
s1 = Signal()
|
||||
f1 = Fragment()
|
||||
f1.add_driver(s1, "sync")
|
||||
f1.add_statements("sync", s1.eq(1))
|
||||
|
||||
cd_por = ClockDomain("por")
|
||||
cd_sync = ClockDomain("sync")
|
||||
|
|
@ -548,7 +565,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
|
|||
def test_propagate_create_missing_fragment_wrong(self):
|
||||
s1 = Signal()
|
||||
f1 = Fragment()
|
||||
f1.add_driver(s1, "sync")
|
||||
f1.add_statements("sync", s1.eq(1))
|
||||
|
||||
f2 = Fragment()
|
||||
f2.add_domains(ClockDomain("foo"))
|
||||
|
|
@ -566,7 +583,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
self.c2 = Signal()
|
||||
|
||||
self.f1 = Fragment()
|
||||
self.f1.add_statements(self.c1.eq(0))
|
||||
self.f1.add_statements("sync", self.c1.eq(0))
|
||||
self.f1.add_driver(self.s1)
|
||||
self.f1.add_driver(self.c1, "sync")
|
||||
|
||||
|
|
@ -574,7 +591,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
self.f1.add_subfragment(self.f1a, "f1a")
|
||||
|
||||
self.f2 = Fragment()
|
||||
self.f2.add_statements(self.c2.eq(1))
|
||||
self.f2.add_statements("sync", self.c2.eq(1))
|
||||
self.f2.add_driver(self.s1)
|
||||
self.f2.add_driver(self.c2, "sync")
|
||||
self.f1.add_subfragment(self.f2)
|
||||
|
|
@ -594,7 +611,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
(self.f1b, "f1b"),
|
||||
(self.f2a, "f2a"),
|
||||
])
|
||||
self.assertRepr(self.f1.statements, """
|
||||
self.assertRepr(self.f1.statements["sync"], """
|
||||
(
|
||||
(eq (sig c1) (const 1'd0))
|
||||
(eq (sig c2) (const 1'd1))
|
||||
|
|
@ -629,12 +646,12 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
|
||||
self.f2 = Fragment()
|
||||
self.f2.add_driver(self.s1)
|
||||
self.f2.add_statements(self.c1.eq(0))
|
||||
self.f2.add_statements(None, self.c1.eq(0))
|
||||
self.f1.add_subfragment(self.f2)
|
||||
|
||||
self.f3 = Fragment()
|
||||
self.f3.add_driver(self.s1)
|
||||
self.f3.add_statements(self.c2.eq(1))
|
||||
self.f3.add_statements(None, self.c2.eq(1))
|
||||
self.f1.add_subfragment(self.f3)
|
||||
|
||||
def test_conflict_sub_sub(self):
|
||||
|
|
@ -642,7 +659,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
|
||||
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
||||
self.assertEqual(self.f1.subfragments, [])
|
||||
self.assertRepr(self.f1.statements, """
|
||||
self.assertRepr(self.f1.statements[None], """
|
||||
(
|
||||
(eq (sig c1) (const 1'd0))
|
||||
(eq (sig c2) (const 1'd1))
|
||||
|
|
@ -658,12 +675,12 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
self.f1.add_driver(self.s1)
|
||||
|
||||
self.f2 = Fragment()
|
||||
self.f2.add_statements(self.c1.eq(0))
|
||||
self.f2.add_statements(None, self.c1.eq(0))
|
||||
self.f1.add_subfragment(self.f2)
|
||||
|
||||
self.f3 = Fragment()
|
||||
self.f3.add_driver(self.s1)
|
||||
self.f3.add_statements(self.c2.eq(1))
|
||||
self.f3.add_statements(None, self.c2.eq(1))
|
||||
self.f2.add_subfragment(self.f3)
|
||||
|
||||
def test_conflict_self_subsub(self):
|
||||
|
|
@ -671,7 +688,7 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
|
|||
|
||||
self.f1._resolve_hierarchy_conflicts(mode="silent")
|
||||
self.assertEqual(self.f1.subfragments, [])
|
||||
self.assertRepr(self.f1.statements, """
|
||||
self.assertRepr(self.f1.statements[None], """
|
||||
(
|
||||
(eq (sig c1) (const 1'd0))
|
||||
(eq (sig c2) (const 1'd1))
|
||||
|
|
@ -848,11 +865,11 @@ class InstanceTestCase(FHDLTestCase):
|
|||
f.add_domains(cd_sync_norst := ClockDomain(reset_less=True))
|
||||
f.add_ports((i, rst), dir="i")
|
||||
f.add_ports((o1, o2, o3), dir="o")
|
||||
f.add_statements([o1.eq(0)])
|
||||
f.add_statements(None, [o1.eq(0)])
|
||||
f.add_driver(o1, domain=None)
|
||||
f.add_statements([o2.eq(i1)])
|
||||
f.add_statements("sync", [o2.eq(i1)])
|
||||
f.add_driver(o2, domain="sync")
|
||||
f.add_statements([o3.eq(i1)])
|
||||
f.add_statements("sync_norst", [o3.eq(i1)])
|
||||
f.add_driver(o3, domain="sync_norst")
|
||||
|
||||
names = f._assign_names_to_signals()
|
||||
|
|
|
|||
|
|
@ -26,26 +26,35 @@ class DomainRenamerTestCase(FHDLTestCase):
|
|||
def test_rename_signals(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s1.eq(ClockSignal()),
|
||||
ResetSignal().eq(self.s2),
|
||||
self.s3.eq(0),
|
||||
self.s4.eq(ClockSignal("other")),
|
||||
self.s5.eq(ResetSignal("other")),
|
||||
)
|
||||
f.add_statements(
|
||||
"sync",
|
||||
self.s3.eq(0),
|
||||
)
|
||||
f.add_driver(self.s1, None)
|
||||
f.add_driver(self.s2, None)
|
||||
f.add_driver(self.s3, "sync")
|
||||
|
||||
f = DomainRenamer("pix")(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s1) (clk pix))
|
||||
(eq (rst pix) (sig s2))
|
||||
(eq (sig s3) (const 1'd0))
|
||||
(eq (sig s4) (clk other))
|
||||
(eq (sig s5) (rst other))
|
||||
)
|
||||
""")
|
||||
self.assertRepr(f.statements["pix"], """
|
||||
(
|
||||
(eq (sig s3) (const 1'd0))
|
||||
)
|
||||
""")
|
||||
self.assertFalse("sync" in f.statements)
|
||||
self.assertEqual(f.drivers, {
|
||||
None: SignalSet((self.s1, self.s2)),
|
||||
"pix": SignalSet((self.s3,)),
|
||||
|
|
@ -54,12 +63,13 @@ class DomainRenamerTestCase(FHDLTestCase):
|
|||
def test_rename_multi(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s1.eq(ClockSignal()),
|
||||
self.s2.eq(ResetSignal("other")),
|
||||
)
|
||||
|
||||
f = DomainRenamer({"sync": "pix", "other": "pix2"})(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s1) (clk pix))
|
||||
(eq (sig s2) (rst pix2))
|
||||
|
|
@ -86,12 +96,13 @@ class DomainRenamerTestCase(FHDLTestCase):
|
|||
f = Fragment()
|
||||
f.add_domains(cd_pix)
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s1.eq(ResetSignal(allow_reset_less=True)),
|
||||
)
|
||||
|
||||
f = DomainRenamer("pix")(f)
|
||||
f = DomainLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd0))
|
||||
)
|
||||
|
|
@ -151,11 +162,12 @@ class DomainLowererTestCase(FHDLTestCase):
|
|||
f = Fragment()
|
||||
f.add_domains(sync)
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s.eq(ClockSignal("sync"))
|
||||
)
|
||||
|
||||
f = DomainLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s) (sig clk))
|
||||
)
|
||||
|
|
@ -166,11 +178,12 @@ class DomainLowererTestCase(FHDLTestCase):
|
|||
f = Fragment()
|
||||
f.add_domains(sync)
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s.eq(ResetSignal("sync"))
|
||||
)
|
||||
|
||||
f = DomainLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s) (sig rst))
|
||||
)
|
||||
|
|
@ -181,11 +194,12 @@ class DomainLowererTestCase(FHDLTestCase):
|
|||
f = Fragment()
|
||||
f.add_domains(sync)
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s.eq(ResetSignal("sync", allow_reset_less=True))
|
||||
)
|
||||
|
||||
f = DomainLowerer()(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements[None], """
|
||||
(
|
||||
(eq (sig s) (const 1'd0))
|
||||
)
|
||||
|
|
@ -208,6 +222,7 @@ class DomainLowererTestCase(FHDLTestCase):
|
|||
def test_lower_wrong_domain(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s.eq(ClockSignal("xxx"))
|
||||
)
|
||||
|
||||
|
|
@ -220,6 +235,7 @@ class DomainLowererTestCase(FHDLTestCase):
|
|||
f = Fragment()
|
||||
f.add_domains(sync)
|
||||
f.add_statements(
|
||||
None,
|
||||
self.s.eq(ResetSignal("sync"))
|
||||
)
|
||||
|
||||
|
|
@ -368,12 +384,13 @@ class ResetInserterTestCase(FHDLTestCase):
|
|||
def test_reset_default(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
"sync",
|
||||
self.s1.eq(1)
|
||||
)
|
||||
f.add_driver(self.s1, "sync")
|
||||
|
||||
f = ResetInserter(self.c1)(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
(switch (sig c1)
|
||||
|
|
@ -384,18 +401,20 @@ class ResetInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_reset_cd(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s1.eq(1),
|
||||
self.s2.eq(0),
|
||||
)
|
||||
f.add_statements("sync", self.s1.eq(1))
|
||||
f.add_statements("pix", self.s2.eq(0))
|
||||
f.add_domains(ClockDomain("sync"))
|
||||
f.add_driver(self.s1, "sync")
|
||||
f.add_driver(self.s2, "pix")
|
||||
|
||||
f = ResetInserter({"pix": self.c1})(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
)
|
||||
""")
|
||||
self.assertRepr(f.statements["pix"], """
|
||||
(
|
||||
(eq (sig s2) (const 1'd0))
|
||||
(switch (sig c1)
|
||||
(case 1 (eq (sig s2) (const 1'd1)))
|
||||
|
|
@ -405,13 +424,11 @@ class ResetInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_reset_value(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s2.eq(0)
|
||||
)
|
||||
f.add_statements("sync", self.s2.eq(0))
|
||||
f.add_driver(self.s2, "sync")
|
||||
|
||||
f = ResetInserter(self.c1)(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s2) (const 1'd0))
|
||||
(switch (sig c1)
|
||||
|
|
@ -422,13 +439,11 @@ class ResetInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_reset_less(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s3.eq(0)
|
||||
)
|
||||
f.add_statements("sync", self.s3.eq(0))
|
||||
f.add_driver(self.s3, "sync")
|
||||
|
||||
f = ResetInserter(self.c1)(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s3) (const 1'd0))
|
||||
(switch (sig c1)
|
||||
|
|
@ -447,13 +462,11 @@ class EnableInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_enable_default(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s1.eq(1)
|
||||
)
|
||||
f.add_statements("sync", self.s1.eq(1))
|
||||
f.add_driver(self.s1, "sync")
|
||||
|
||||
f = EnableInserter(self.c1)(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
(switch (sig c1)
|
||||
|
|
@ -464,17 +477,19 @@ class EnableInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_enable_cd(self):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s1.eq(1),
|
||||
self.s2.eq(0),
|
||||
)
|
||||
f.add_statements("sync", self.s1.eq(1))
|
||||
f.add_statements("pix", self.s2.eq(0))
|
||||
f.add_driver(self.s1, "sync")
|
||||
f.add_driver(self.s2, "pix")
|
||||
|
||||
f = EnableInserter({"pix": self.c1})(f)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
)
|
||||
""")
|
||||
self.assertRepr(f.statements["pix"], """
|
||||
(
|
||||
(eq (sig s2) (const 1'd0))
|
||||
(switch (sig c1)
|
||||
(case 0 (eq (sig s2) (sig s2)))
|
||||
|
|
@ -484,21 +499,17 @@ class EnableInserterTestCase(FHDLTestCase):
|
|||
|
||||
def test_enable_subfragment(self):
|
||||
f1 = Fragment()
|
||||
f1.add_statements(
|
||||
self.s1.eq(1)
|
||||
)
|
||||
f1.add_statements("sync", self.s1.eq(1))
|
||||
f1.add_driver(self.s1, "sync")
|
||||
|
||||
f2 = Fragment()
|
||||
f2.add_statements(
|
||||
self.s2.eq(1)
|
||||
)
|
||||
f2.add_statements("sync", self.s2.eq(1))
|
||||
f2.add_driver(self.s2, "sync")
|
||||
f1.add_subfragment(f2)
|
||||
|
||||
f1 = EnableInserter(self.c1)(f1)
|
||||
(f2, _), = f1.subfragments
|
||||
self.assertRepr(f1.statements, """
|
||||
self.assertRepr(f1.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
(switch (sig c1)
|
||||
|
|
@ -506,7 +517,7 @@ class EnableInserterTestCase(FHDLTestCase):
|
|||
)
|
||||
)
|
||||
""")
|
||||
self.assertRepr(f2.statements, """
|
||||
self.assertRepr(f2.statements["sync"], """
|
||||
(
|
||||
(eq (sig s2) (const 1'd1))
|
||||
(switch (sig c1)
|
||||
|
|
@ -542,9 +553,7 @@ class _MockElaboratable(Elaboratable):
|
|||
|
||||
def elaborate(self, platform):
|
||||
f = Fragment()
|
||||
f.add_statements(
|
||||
self.s1.eq(1)
|
||||
)
|
||||
f.add_statements("sync", self.s1.eq(1))
|
||||
f.add_driver(self.s1, "sync")
|
||||
return f
|
||||
|
||||
|
|
@ -569,7 +578,7 @@ class TransformedElaboratableTestCase(FHDLTestCase):
|
|||
self.assertIs(te1, te2)
|
||||
|
||||
f = Fragment.get(te2, None)
|
||||
self.assertRepr(f.statements, """
|
||||
self.assertRepr(f.statements["sync"], """
|
||||
(
|
||||
(eq (sig s1) (const 1'd1))
|
||||
(switch (sig c1)
|
||||
|
|
|
|||
|
|
@ -889,7 +889,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
|
||||
m = Module()
|
||||
connect(m, src=src, snk=snk)
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements], [
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements[None]], [
|
||||
'(eq (sig snk__addr) (sig src__addr))',
|
||||
'(eq (sig snk__cycle) (sig src__cycle))',
|
||||
'(eq (sig src__r_data) (sig snk__r_data))',
|
||||
|
|
@ -903,7 +903,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
a=Const(1)),
|
||||
q=NS(signature=Signature({"a": In(1)}),
|
||||
a=Const(1)))
|
||||
self.assertEqual(m._statements, [])
|
||||
self.assertEqual(m._statements, {})
|
||||
|
||||
def test_nested(self):
|
||||
m = Module()
|
||||
|
|
@ -912,7 +912,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
a=NS(signature=Signature({"f": Out(1)}), f=Signal(name='p__a'))),
|
||||
q=NS(signature=Signature({"a": In(Signature({"f": Out(1)}))}),
|
||||
a=NS(signature=Signature({"f": Out(1)}).flip(), f=Signal(name='q__a'))))
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements], [
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements[None]], [
|
||||
'(eq (sig q__a) (sig p__a))'
|
||||
])
|
||||
|
||||
|
|
@ -931,7 +931,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
g=Signal(name="q__b__g"),
|
||||
f=Signal(name="q__b__f")),
|
||||
a=Signal(name="q__a")))
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements], [
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements[None]], [
|
||||
'(eq (sig q__a) (sig p__a))',
|
||||
'(eq (sig q__b__f) (sig p__b__f))',
|
||||
'(eq (sig q__b__g) (sig p__b__g))',
|
||||
|
|
@ -942,7 +942,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
|
||||
m = Module()
|
||||
connect(m, p=sig.create(path=('p',)), q=sig.flip().create(path=('q',)))
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements], [
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements[None]], [
|
||||
'(eq (sig q__a__0) (sig p__a__0))',
|
||||
'(eq (sig q__a__1) (sig p__a__1))'
|
||||
])
|
||||
|
|
@ -952,7 +952,7 @@ class ConnectTestCase(unittest.TestCase):
|
|||
|
||||
m = Module()
|
||||
connect(m, p=sig.create(path=('p',)), q=sig.flip().create(path=('q',)))
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements], [
|
||||
self.assertEqual([repr(stmt) for stmt in m._statements[None]], [
|
||||
'(eq (sig q__a__0__0) (sig p__a__0__0))',
|
||||
])
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
|
||||
stmt = stmt(osig, *isigs)
|
||||
frag = Fragment()
|
||||
frag.add_statements(stmt)
|
||||
frag.add_statements(None, stmt)
|
||||
for signal in flatten(s._lhs_signals() for s in Statement.cast(stmt)):
|
||||
frag.add_driver(signal)
|
||||
|
||||
|
|
@ -1045,9 +1045,10 @@ class SimulatorRegressionTestCase(FHDLTestCase):
|
|||
|
||||
def test_bug_595(self):
|
||||
dut = Module()
|
||||
dummy = Signal()
|
||||
with dut.FSM(name="name with space"):
|
||||
with dut.State(0):
|
||||
pass
|
||||
dut.d.comb += dummy.eq(1)
|
||||
sim = Simulator(dut)
|
||||
with self.assertRaisesRegex(NameError,
|
||||
r"^Signal 'bench\.top\.name with space_state' contains a whitespace character$"):
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue