back.verilog: do not rename internal signals.

_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.

nmigen/back/verilog.py

@@ -28,7 +28,7 @@ proc_arst
 proc_dff
 proc_clean
 memory_collect
-write_verilog
+write_verilog -norename
 # Make sure there are no undriven wires in generated RTLIL.
 proc
 select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d