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back.verilog: do not rename internal signals.

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_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
This commit is contained in:
whitequark 2018-12-22 00:53:40 +00:00
parent 5361b4c22b
commit 6ee80408bb
1 changed files with 1 additions and 1 deletions
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nmigen/back/verilog.py
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@ -28,7 +28,7 @@ proc_arst
proc_dff proc_dff
proc_clean proc_clean
memory_collect memory_collect
write_verilog write_verilog -norename
# Make sure there are no undriven wires in generated RTLIL. # Make sure there are no undriven wires in generated RTLIL.
proc proc
select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d