hdl.ast: Add AnyConst and AnySeq value types.
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@ -1,4 +1,4 @@
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from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume
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from .hdl.ast import Value, Const, C, AnyConst, AnySeq, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume
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from .hdl.dsl import Module
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from .hdl.dsl import Module
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from .hdl.cd import ClockDomain
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from .hdl.cd import ClockDomain
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from .hdl.ir import Fragment, Instance
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from .hdl.ir import Fragment, Instance
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@ -9,7 +9,7 @@ from ..tools import *
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__all__ = [
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__all__ = [
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"Value", "Const", "C", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
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"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
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"Array", "ArrayProxy",
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"Array", "ArrayProxy",
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"Signal", "ClockSignal", "ResetSignal",
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"Signal", "ClockSignal", "ResetSignal",
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"Statement", "Assign", "Assert", "Assume", "Switch", "Delay", "Tick",
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"Statement", "Assign", "Assert", "Assume", "Switch", "Delay", "Tick",
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@ -254,6 +254,32 @@ class Const(Value):
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C = Const # shorthand
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C = Const # shorthand
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class AnyValue(Value):
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def __init__(self, shape):
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super().__init__(src_loc_at=0)
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if isinstance(shape, int):
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shape = shape, False
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self.nbits, self.signed = shape
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if not isinstance(self.nbits, int) or self.nbits < 0:
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raise TypeError("Width must be a non-negative integer, not '{!r}'", self.nbits)
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def shape(self):
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return self.nbits, self.signed
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def _rhs_signals(self):
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return ValueSet()
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class AnyConst(AnyValue):
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def __repr__(self):
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return "(anyconst {}'{})".format(self.nbits, "s" if self.signed else "")
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class AnySeq(AnyValue):
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def __repr__(self):
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return "(anyseq {}'{})".format(self.nbits, "s" if self.signed else "")
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class Operator(Value):
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class Operator(Value):
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def __init__(self, op, operands, src_loc_at=0):
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def __init__(self, op, operands, src_loc_at=0):
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super().__init__(src_loc_at=1 + src_loc_at)
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super().__init__(src_loc_at=1 + src_loc_at)
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