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vendor.xilinx_{7series,ultrascale}: don't use write_verilog -decimal.

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In commit 892cff05, `-decimal` was used when writing Verilog for
Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *)
differently in violation of Verilog LRM. However, it is possible
to avoid that workaround by using (* keep="TRUE" *). Do that,
and remove `-decimal` to avoid special-casing 32-bit constants.

Refs #373.
This commit is contained in:
whitequark 2020-05-21 08:57:30 +00:00
parent 3420b683a3
commit 702e41ba3c
2 changed files with 6 additions and 10 deletions
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8
nmigen/vendor/xilinx_7series.py vendored
View file

@ -66,15 +66,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
[ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}" [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
{{emit_commands("sh")}} {{emit_commands("sh")}}
""", """,
# Vivado doesn't like constructs like (* keep = 32'd1 *), even though they mean the same
# thing as (* keep = 1 *); use -decimal to work around that.
"{{name}}.v": r""" "{{name}}.v": r"""
/* {{autogenerated}} */ /* {{autogenerated}} */
{{emit_verilog(["-decimal"])}} {{emit_verilog()}}
""", """,
"{{name}}.debug.v": r""" "{{name}}.debug.v": r"""
/* {{autogenerated}} */ /* {{autogenerated}} */
{{emit_debug_verilog(["-decimal"])}} {{emit_debug_verilog()}}
""", """,
"{{name}}.tcl": r""" "{{name}}.tcl": r"""
# {{autogenerated}} # {{autogenerated}}
@ -181,7 +179,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
def add_clock_constraint(self, clock, frequency): def add_clock_constraint(self, clock, frequency):
super().add_clock_constraint(clock, frequency) super().add_clock_constraint(clock, frequency)
clock.attrs["keep"] = 1 clock.attrs["keep"] = "TRUE"
def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False): def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q): def get_dff(clk, d, q):

8
nmigen/vendor/xilinx_ultrascale.py vendored
View file

@ -66,15 +66,13 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
[ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}" [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
{{emit_commands("sh")}} {{emit_commands("sh")}}
""", """,
# Vivado doesn't like constructs like (* keep = 32'd1 *), even though they mean the same
# thing as (* keep = 1 *); use -decimal to work around that.
"{{name}}.v": r""" "{{name}}.v": r"""
/* {{autogenerated}} */ /* {{autogenerated}} */
{{emit_verilog(["-decimal"])}} {{emit_verilog()}}
""", """,
"{{name}}.debug.v": r""" "{{name}}.debug.v": r"""
/* {{autogenerated}} */ /* {{autogenerated}} */
{{emit_debug_verilog(["-decimal"])}} {{emit_debug_verilog()}}
""", """,
"{{name}}.tcl": r""" "{{name}}.tcl": r"""
# {{autogenerated}} # {{autogenerated}}
@ -181,7 +179,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
def add_clock_constraint(self, clock, frequency): def add_clock_constraint(self, clock, frequency):
super().add_clock_constraint(clock, frequency) super().add_clock_constraint(clock, frequency)
clock.attrs["keep"] = 1 clock.attrs["keep"] = "TRUE"
def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False): def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q): def get_dff(clk, d, q):